7C10 Search Results

Contextual Info: ^ SS WS CYPRESS PRELIMINARY , .^= 131,072 x 8 Static R/W RAM SEMICONDUCTOR Features Functional Description • H ighspeed — tAA = 25 ns T h e CY 7C108 an d CY 7C109 are high-perform anceC M O S static R A M s organized as 131,072 w ords by 8 bits. Easy m em ory ex­

Contextual Info: 7C101A: 11-25-91 Revision: Thursday, February 18,1993 7C101A 7C102A k ' Vwt S3 « 3 PRELIMINARY 7J= CYPRESS SEMICONDUCTOR 256K x 4 Static RAM with Separate I/O Features Functional Description • Highspeed — tAA = 12 ns • Transparent write 7C101A

automatic change over switch circuit diagram

Abstract: CY7C1007 CY7C1007-12PC CY7C1007-12VC CY7C1007-15PC R1480
Contextual Info: 1CY 7C10 07 PRELIMINARY 7C1007 1M x 1 Static RAM Features is provided by an active LOW chip enable CE and three-state drivers. The device has an automatic power-down feature that reduces power consumption by more than 65% when deselected. • High speed

transistor c1016

Abstract: c1016 CY7C1016 C10161
Contextual Info: fax id: 1057 1CY 7C10 16 ADVANCED INFORMATION 7C1016 256K x 4 Static RAM Features output enable OE , and three-state drivers. The device has an automatic power-down feature that significantly reduces power consumption when deselected. • High speed — tAA = 10 ns

80486 microprocessor block diagram and pin diagrams

Abstract: EQUIVALENT cd 1031 cs cd 1031 80486 microprocessor block diagram and pin diagram 80486 microprocessor pin out diagram block diagram of processor 80486 EQUIVALENT cd 1031 80486 microprocessor description 80486 microprocessor features 80486* diagram circuits
Contextual Info: 7C1031 7C1032 64K x 18 Synchronous Cache RAM Features Functional Description • Supports 66-MHz Pentium microprocessor cache systems with zero wait states • 64K by 18 common I/O • Fast clock-to-output times — 8.5 ns • Two-bit wraparound counter supporting Pentium microprocessor and 486 burst sequence 7C1031

550mi

Contextual Info: 7c1021: March 31,1995 Revised: June 25,1996 7C1021 64K x 16 Static RAM ADVANCED INFORMATION Features Functional Description The 7C1021 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW chip enable

CY7C1019

Contextual Info: 1CY 7C10 19 ADVANCED INFORMATION 7C1019 128K x 8 Static RAM Features • High speed — tAA = 10 ns • CMOS for optimum speed/power • Center power/ground pinout • Automatic power-down when deselected • Easy memory expansion with CE and OE options

CY7C1009

Contextual Info: 1CY 7C10 09 PRELIMINARY 7C1009 128K x 8 Static RAM Features • High speed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 1020 mW • Low standby power — 250 mW • 2.0V data retention optional — 100 µW • Available in 450 x 550-mil LCC

CY7C1021V30

Abstract: CY7C1021V30-15BSI
Contextual Info: fax id: 1083 1CY 7C10 21 V ADVANCED INFORMATION 7C1021V30 64K x 16 Static RAM Features • 3.0V operation 2.7V–3.3V • High speed — tAA = 15 ns • CMOS for optimum speed/power • Low active power (L version) — 462 mW (max.) • Low CMOS Standby Power (L version)

CY7C1016

Abstract: A0231 A2429 C10161
Contextual Info: 7c1006: 11-25-91 Revision: April 10, 1995 ADVANCED INFORMATION CMOS static RAM organized as 262,144 words by 4 bits. Easy memory expansion is D provided by an active LOW chip enable Ċ CE , an active LOW output enable (OE), and threeĆstate drivers. The device has an

CY7C1021

Abstract: 7c1021
Contextual Info: 7c1021: March 31, 1995 Revised: June 25, 1996 ADVANCED INFORMATION 7C1021 64K x 16 Static RAM Features D Functional Description The 7C1021 is a highĆperformance CMOS static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW chip enable

r32d

Abstract: CY7C1049 140C JESD22 CY7C1048
Contextual Info: Cypress Semiconductor Qualification Report QTP# 97344 VERSION 1.0 March, 1998 R32D Technology - Metal 2 Hot Aluminum Cypress Semiconductor, Inc. R32D Technology - Hot Aluminum Metal 2 - Fab4 Device: 7C1049 7C1049A Package: SOJ QTP# 97344, V. 1.0 Page 2 of 7

7C109A

Abstract: CY7C109
Contextual Info: Cypress Semiconductor Qualification Report QTP# 98064 VERSION 1.0 April, 1998 1 Meg SRAM, R42HD Technology, Fab 4 Qualification 7C109/7C1009 128K x 8 SRAM 5V Operation Cypress Semiconductor, Inc. 128K x 8 SRAM - R42DH Technology - Fab 4 Device: 7C109 (7C109H)

80486 microprocessor block diagram and pin diagrams

Abstract: 80486 microprocessor block diagram and pin diagram r2868 EQUIVALENT cd 1031 intel 80486 CY7C1031 CY7C1032 80486 microprocessor 80486 microprocessor pin out diagram
Contextual Info: 1CY 7C10 32 7C1031 7C1032 PRELIMINARY 64K x 18 Synchronous Cache RAM Features Functional Description • Supports 66-MHz Pentium microprocessor cache systems with zero wait states • 64K by 18 common I/O • Fast clock-to-output times — 8.5 ns • Two-bit wraparound counter supporting Pentium microprocessor and 486 burst sequence 7C1031

CY7C102-35PC

Abstract: 7C101-35 HO- 21C L7535 2C1012
Contextual Info: CYPRESS SE MI CO NDU CTOR MbE D B 250^5 GOObSflö □ E3CYP 'T - ^ - V b A O ,V ilT ' '-• * •' * ' CYPRESS SEMICONDUCTOR 262,144 x 4 Static RfW RAM with Separate I/O Features Functional Description • H ighspeed — tAA = 25 ns • Ttgnsparent write (7C101

CY7C1021V33-12ZC

Abstract: cy7c1021v33-15zi CY7C1021V33-10VC CY7C1021V CY7C1021V33-10ZC
Contextual Info: fax id: 1077 1CY 7C10 21 V PRELIMINARY 7C1021V 64K x 16 Static RAM Features Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is

M5M27C100K

Abstract: 27C100K m5m27c100 M5M27C100K-15 M5M27C100K15 M5M27C100K-2
Contextual Info: MITSUBISHI LSIs M5M2 7C100K, -12, -15, -2/ 7C100JK -12,-15,-2 1 0 4 8 S 7 6 - B IT 1 3 1 0 7 2 - WORD B Y 8-B IT CMOS ER A S A B LE AND E LE C T R IC A LLY REPROGRAM M ABLE ROM DESCRIPTION The Mitsubishi 7C100K, J K is a high-speed 1048576bit ultraviolet erasable and electrically reprogrammable read

Contextual Info: 7c10 0 6 :1 1-25-91 Revision: Tuesday, December 22,1992 7C1006 PRELIMINARY CYPRESS sÈr SEMICONDUCTOR 256K x 4 Static RAM Features Functional Description • Highspeed — tAA = 12 ns • CMOS for optimum speed/power The 7C1006 is a high-performance CMOS static RAM organized as 262,144

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR 128Kx 8 Static RAM Features Functional Description • High speed T h e C Y 7C109A is a high-perform ance C M O S static R A M organized as 131,072 w ords by 8 bits. Easy m em ory expansion is provided by an active L O W chip enable

Contextual Info: MITSUBISHI LSIs M5M2 7C100K, -12, -15, -2/ 7C100JK -12, -15,-2 1048576-BIT 131072-WORD BY 8-BIT CMOS ERASABLE AND ELECTRICALLY REPROGRAMMABLE ROM DESCRIPTION The M its u b is h i M 5 M 2 7 C 1 0 0 K , J K is a high-speed 10 48576- PIN CONFIGURATION (TOP VIEW)

V32 Package

Abstract: CY7C1001 CY7C1002 7C10011
Contextual Info: PRELIMINARY ’# CYPRESS • H igh speed — tAA = 12 ns • T ransparent w rite 7C1001 • C M O S for optim um speed/pow er • Low active power — 910 rnW • Low standby power — 275 mW • 2.0V data retention (optional) — lOfl |iW • 256K x 4 Static RAM

SOJ package MSL

Abstract: 7C109A CY7C109 JESD22 R42HD R42HD FAB4
Contextual Info: Cypress Semiconductor Qualification Report QTP# 98085 VERSION 1.0 June, 1998 1 Meg SRAM, R42HD Technology, Hot Aluminum 7C109/7C1009 128K x 8 SRAM 5V Operation Cypress Semiconductor, Inc. 1 Meg SRAM - R42HD Technology, Hot Al - Fab 4 Device: 7C109 (7C109H)

CY7C1020

Contextual Info: 7C10 7C1020 32K x 16 Static RAM Features BLE is LOW, then data from I/O pins (I/O 1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 9 through I/O16) is written into the location

Contextual Info: 7C106A PRELIMINARY CYPRESS SEMICONDUCTOR Features Functional Description • High speed T he C Y 7C106A is a high-perform ance C M O S static R A M organized as 262,144 w ords by 4 bits. Easy m em ory expansion is provided by an active L O W chip enable