CY7C109 Search Results

AB26S

Abstract: 7C109A CY7C109 CY7C109A
Contextual Info: CY7C109A PRELIMINARY l ^wSSQBBSf S S ySSt Ì p YJe JkP XRI- XjiïJF ^ 128KX 8 Static RAM Features Functional Description • H ighspeed The CY7C109A is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable

Contextual Info: fax id: 1047 CY7C109 CY7C1009 ^C YPR ESS 128K x 8 Static RAM active HIGH chip enable CE 2 , an active LOW output enable (OE), and three-state drivers. Writing to the device is accom plished by taking chip enable one (CE-|) and write enable (WE) inputs LOW and chip enable two (CE 2 ) input HIGH. Data on

cy7c109l-15vi

Abstract: CY7C109L15VI CY7C109L CY7C1009 CY7C109 CY7C1009-15VI cy7c109-15zc CY7C109-15VI
Contextual Info: CY7C109 CY7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW max., 12 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low-power version) • 2.0V Data Retention (Low-power version) • Automatic power-down when deselected

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 38-05038 Spec Title: CY7C109B, CY7C1009B 128K X 8 STATIC RAM Sunset Owner: Prashanth Jnanendra PRAS Replaced by: NONE CY7C109B CY7C1009B 128K x 8 Static RAM Functional Description[1] Features • High speed The CY7C109B/CY7C1009B is a high-performance CMOS

Contextual Info: CY7C109D CY7C1009D 1-Mbit 128 K x 8 Static RAM 1-Mbit (128 K × 8) Static RAM Features • Pin- and function-compatible with CY7C109B/CY7C1009B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA

CY7C1009

Abstract: CY7C109
Contextual Info: fax id: 1047 CY7C109 CY7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW max., 12 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power version) • Automatic power-down when deselected

Contextual Info: CY7C109 CYPRESS F u n c tio n a l D escrip tio n F e a tu re s • High speed — tAA = 20 ns • • C M O S for optim um speed/pow er Low active power — 770 mW • Low standby power — 165 mW • A utom atic power-down when deselected • T T L -com patible inputs and outputs

7C109A

Abstract: CY7C106A CY7C109 JESD22
Contextual Info: Qualification Report December 1996 QTP# 96053/96081, Version 1.2 1 Meg SRAM - R28 Technology CY7C106A 256K x 4 Static RAM CY7C109 128K x 8 Static RAM PRODUCT DESCRIPTION for qualification Information provided in this document is intended for generic qualification and technically describes the Cypress part

7C109A

Abstract: CY7C109
Contextual Info: Cypress Semiconductor Qualification Report QTP# 98064 VERSION 1.0 April, 1998 1 Meg SRAM, R42HD Technology, Fab 4 Qualification CY7C109/CY7C1009 128K x 8 SRAM 5V Operation Cypress Semiconductor, Inc. 128K x 8 SRAM - R42DH Technology - Fab 4 Device: CY7C109 (7C109H)

Contextual Info: CY7C109B CY7C1009B 128K x 8 Static RAM Features put Enable OE , and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O 0 through I/O 7) is then

CY7C1009V33

Abstract: CY7C109V33
Contextual Info: 3 CY7C1009V33 CY7C109V33 PRELIMINARY 128K x 8 Static RAM Features memory expansion is provided by an active LOW chip enable CE1 , an active HIGH chip enable (CE2), an active LOW output enable (OE), and three-state drivers. Writing to the device is accomplished by taking chip enable one (CE1) and write

G 1009l

Abstract: CY7C1009 CY7C109
Contextual Info: fax id: 1047 CY7C109 CY7C1009 CYPRESS 128K x 8 Static RAM Features active HIG H chip enable C E 2 , an active LO W ou tput enable (OE), and three -state drivers. W riting to the device is a cco m ­ plished by takin g chip enable one (CE-|) and w rite enable (WE)

V32 Package

Abstract: CY7C1009V33 CY7C109V33
Contextual Info: CY7C1009V33 CY7C109V33 iF c y p r e s s 128K x 8 Static RAM Features memory expansion is provided by an active LOW Chip Enable CE-| , an active HIGH Chip Enable (CE2), an active LOW Out­ put Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable one (CE-|) and Write

Contextual Info: CY7C109D CY7C1009D 1-Mbit 128K x 8 Static RAM Functional Description [1] Features • Pin- and function-compatible with CY7C109B/CY7C1009B • High speed — tAA = 10 ns • Low active power — ICC = 80 mA @ 10 ns • Low CMOS standby power The CY7C109D/CY7C1009D is a high-performance CMOS

SOJ package MSL

Abstract: 7C109A CY7C109 JESD22 R42HD R42HD FAB4
Contextual Info: Cypress Semiconductor Qualification Report QTP# 98085 VERSION 1.0 June, 1998 1 Meg SRAM, R42HD Technology, Hot Aluminum CY7C109/CY7C1009 128K x 8 SRAM 5V Operation Cypress Semiconductor, Inc. 1 Meg SRAM - R42HD Technology, Hot Al - Fab 4 Device: CY7C109 (7C109H)

CY7C1009D

Abstract: CY7C109D TSOP 66 thermal resistance
Contextual Info: CY7C109D CY7C1009D 1-Mbit 128 K x 8 Static RAM Features Functional Description [1] • Pin- and function-compatible with CY7C109B/CY7C1009B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA

7C109A-20

Abstract: 7C109A
Contextual Info: CY7C109A PRELIMINARY S F # SEMICONDUCTOR 128K x 8 Static RAM Features Functional Description • High speed — tAA = 12 ns • CMOS for optimum speed/power The CY7C109A is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is

cy7c109bnl

Abstract: CY7C109BNL-15VC CY7C1009BN CY7C109BN
Contextual Info: CY7C109BN CY7C1009BN 128K x 8 Static RAM Functional Description[1] Features • High speed The CY7C109BN/CY7C1009BN is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE1 , an active HIGH Chip Enable (CE2), an active LOW

CY7C1009

Abstract: CY7C109 7C109-25 cypress cy7c109-20zi
Contextual Info: CY7C109 CY7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW max., 12 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power version) • Automatic power-down when deselected

CY7C1009V33

Abstract: CY7C109V33
Contextual Info: CY7C1009V33 CY7C109V33 128K x 8 Static RAM Features memory expansion is provided by an active LOW Chip Enable CE1 , an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable one (CE1) and Write

CY7C109L

Abstract: CY7C109L-15VI 7C1009 A15C CY7C1009 CY7C109
Contextual Info: CY7C109 CY7C1009 CYPRESS 128K Features 8 Static RAM able OE , and th re e -sta te drivers. W ritin g to the device is ac­ com p lish ed by takin g C hip Enable O ne (CE-|) and W rite En­ able (W E) inputs LO W and C hip Enable Two (CEg) input HIGH. D ata on the eigh t I/O pins (l/O 0 throu gh l/ 0 7) is then w ritten

CY7C1009D-10VXI

Abstract: CY7C109D-10VXI a5 gnd
Contextual Info: CY7C109D CY7C1009D 1-Mbit 128K x 8 Static RAM Functional Description [1] Features • Pin- and function-compatible with CY7C109B/CY7C1009B • High speed — tAA = 10 ns • Low active power — ICC = 80 mA @ 10 ns • Low CMOS standby power The CY7C109D/CY7C1009D is a high-performance CMOS

CY7C1009B

Abstract: CY7C109B
Contextual Info: CY7C109B CY7C1009B 128K x 8 Static RAM Features put Enable OE , and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O 0 through I/O 7) is then

7C109A

Abstract: CY7C106A CY7C109 JESD22
Contextual Info: Qualification Report December 1996, QTP# 96313, Version 1.1 1 Meg SRAM - R28 Technology CY7C106A 256K x 4 Static RAM CY7C109 128K x 8 Static RAM PRODUCT DESCRIPTION for qualification Information provided in this document is intended for generic qualification and technically describes the Cypress part