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Infineon Technologies AG CY7C1021D-10ZSXI SRAM Chip Async Single 5V 1M-Bit 64K x 16 10ns 44-Pin TSOP-II Tray - Trays (Alt: CY7C1021D-10ZSXI)
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Avnet Americas	CY7C1021D-10ZSXI	Tray	412		675	1 - 10 - 100 - 1000 - 10000 -	Buy Now
Newark	CY7C1021D-10ZSXI	Bulk			1	1 $4.95 10 $4.72 100 $4.29 1000 $3.79 10000 $3.79	Buy Now
TME	CY7C1021D-10ZSXI				1	1 $3.76 10 $3.76 100 $2.72 1000 $2.64 10000 $2.64	Get Quote
Infineon Technologies AG CY7C1021D-10VXI - Rail/Tube (Alt: CY7C1021D-10VXI)
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Avnet Americas	CY7C1021D-10VXI	Tube	40		510	1 - 10 - 100 - 1000 - 10000 -	Buy Now
Newark	CY7C1021D-10VXI	Bulk	410		1	1 $5.14 10 $5.02 100 $4.55 1000 $4.35 10000 $4.35	Buy Now
TME	CY7C1021D-10VXI		32		1	1 $2.26 10 $2.26 100 $2.13 1000 $1.90 10000 $1.90	Buy Now
Infineon Technologies AG CY7C1021DV33-10VXI SRAM Chip Async Single Port 1Mbit 64K X 16Bit 3.3V 44-Pin SOJ Bulk - Rail/Tube (Alt: CY7C1021DV33-10VXI)
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Avnet Americas ()	CY7C1021DV33-10VXI	Tube			510	1 - 10 - 100 - 1000 $1.67 10000 $1.43	Get Quote
	CY7C1021DV33-10VXI	Tube		26 Weeks	510	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Newark	CY7C1021DV33-10VXI	Bulk	61		1	1 $3.27 10 $3.20 100 $3.01 1000 $2.88 10000 $2.88	Buy Now
TME	CY7C1021DV33-10VXI				17	1 - 10 - 100 $2.06 1000 $2.06 10000 $2.06	Get Quote
Flip Electronics	CY7C1021DV33-10VXI		6,794			1 $1.10 10 $1.10 100 $1.10 1000 $1.10 10000 $1.10	Get Quote
Infineon Technologies AG CY7C1021D-10ZSXIT SRAM Chip Async Single 5V 1M-Bit 64K x 16 10ns 44-Pin TSOP-II T/R - Tape and Reel (Alt: CY7C1021D-10ZSXIT)
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Avnet Americas	CY7C1021D-10ZSXIT	Tape & Reel			1,000	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Newark	CY7C1021D-10ZSXIT	Bulk			1	1 $5.12 10 $4.80 100 $4.49 1000 $4.23 10000 $4.23	Buy Now
TME	CY7C1021D-10ZSXIT				1,000	1 - 10 - 100 - 1000 $3.14 10000 $3.14	Get Quote
Flip Electronics	CY7C1021D-10ZSXIT		2,025			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Vishay Intertechnologies RNR57C1021FSBSL1 - Bulk (Alt: RNR57C1021FSBSL1)
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Avnet Americas	RNR57C1021FSBSL1	Bulk			25	1 - 10 - 100 $113.66 1000 $110.75 10000 $110.75	Buy Now

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7C1021 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
550mi Contextual Info: 7c1021: March 31,1995 Revised: June 25,1996 7C1021 64K x 16 Static RAM ADVANCED INFORMATION Features Functional Description The 7C1021 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW chip enable	OCR Scan	7c1021 550-mil cy7c1021 i/o13 +5i/o10 7c1021--12 7c1021--15 7c1021--20 550mi	PDF
CY7C1021 Abstract: 7c1021 Contextual Info: 7c1021: March 31, 1995 Revised: June 25, 1996 ADVANCED INFORMATION 7C1021 64K x 16 Static RAM Features D Functional Description The 7C1021 is a highĆperformance CMOS static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW chip enable	Original	7c1021 cy7c1021 i/o15 7c1021-12 +27c1021-15 7c1021-20	PDF
7C1021 Abstract: C2223 ge639 A12C CY7C1021 Contextual Info: CYPRESS Features • 12 ns • C M O S for optim um speed/pow er • L ow active power — 1020 mW • A vailable in 450 x 550-m il LCC • A utom atic power-down w hen deselected • E asy m em ory exp an sion w ith C Ej, CE 2, and O E options 7C1021 64K x 16 Static RAM	OCR Scan	cy7c1021 550-mil l/016 7c1021 +47c102x c2223 ge639 a12c	PDF
Contextual Info: fax id: 1083 C 'i- PRELIMINARY 7C1021V30 64K Features X 16 Static RAM Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BEE) is LOW, then data from I/O pins (l/Oi through l/0 8), is written into the location specified on the address pins (A0	OCR Scan	cy7c1021v30	PDF
Contextual Info: 7C1021 P Yi. PX :V«*1 64K x 16 Static RAM BLE is LOW, then data from I/O pins (l/0-\| through l/0 8), is written into the location specified on the address pins (A0 through A i5). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through I/0 1 6) is written into the location speci	OCR Scan	cy7c1021	PDF
ATPA Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C	Original	cy2147-35c cy7c147-35c cy7c147-45c cy91l22-35c +14cy7c122-35c cy2147-45c cy7c148-35c cy7c148-25c atpa 7130sa100p 24l01 7c263/4-35c 7164s15y cy9122-25 7133sa35j 7142sa55 7130sa55p cy2149-45c	PDF
CY7C1021BN-15VI Abstract: CY7C1021BN Contextual Info: 7C1021BN 7C10211BN 1-Mbit 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0	Original	cy7c1021bn cy7c10211bn i/o16 cy7c1021bn/cy7c10211bn +1cy7c1021bn-15vi	PDF
CY7C1021BN Contextual Info: 7C1021BN 7C10211BN 1-Mbit 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0	Original	cy7c1021bn cy7c10211bn i/o16 cy7c1021bn/cy7c10211bn	PDF
Contextual Info: 7C1021D PRELIMINARY 1-Mbit 64K x 16 Static RAM Features automatic power-down feature that significantly reduces power consumption when deselected. • Pin- and function-compatible with 7C1021B • High speed — tAA = 10 ns • CMOS for optimum speed/power	Original	cy7c1021d cy7c1021b 44-pin 400-mil	PDF
CY7C1021V30 Abstract: CY7C1021V30-15BSI Contextual Info: fax id: 1083 1CY 7C10 21 V ADVANCED INFORMATION 7C1021V30 64K x 16 Static RAM Features • 3.0V operation 2.7V–3.3V • High speed — tAA = 15 ns • CMOS for optimum speed/power • Low active power (L version) — 462 mW (max.) • Low CMOS Standby Power (L version)	Original	cy7c1021v30 cy7c1021v30-15bsi	PDF
CY7C1021BV Abstract: CY7C1021BV33 Contextual Info: 7C1021BV33 7C1021BV33 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable CE and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0	Original	1cy7c1021bv33 cy7c1021bv33 i/o16 cy7c1021bv	PDF
CY7C1021B-15ZSXE Abstract: CY7C1021B-12ZXC CY7C1021B Contextual Info: 7C1021B 1-Mbit 64K x 16 Static RAM Features automatic power-down feature that significantly reduces power consumption when deselected. • Temperature Ranges Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable	Original	cy7c1021b i/o16 cy7c10211b cy7c1021b-15zsxe +1cy7c1021b-12zxc	PDF
CY7C1021V33-15VI Abstract: 1021V-10 CY7C1021V33L-15ZI CY7C1021V33 CY7C1021V CY7C1021V33-12ZC CY7C1021V33L15ZI CY7C1021V33L15BAC CY7C1021V33-12BAI Contextual Info: fax id: 1077 7C1021V 64K x 16 Static RAM Features Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0	Original	cy7c1021v i/o16 cy7c1021v33-15vi 1021v-10 +6cy7c1021v33l-15zi cy7c1021v33 cy7c1021v33-12zc cy7c1021v33l15zi cy7c1021v33l15bac cy7c1021v33-12bai	PDF
7C1021-10 Contextual Info: 7C1021 64K x 16 Static RAM BLE is LOW, then data from I/O pins (l/0-\| through l/Os), is written into the location specified on the address pins (A0 through A 15). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through l/0 16) is written into the location speci	OCR Scan	cy7c1021 44-pin 400-mil 7c1021-10	PDF

CY7C1021V33-12ZC Abstract: cy7c1021v33-15zi CY7C1021V33-10VC CY7C1021V CY7C1021V33-10ZC Contextual Info: fax id: 1077 1CY 7C10 21 V PRELIMINARY 7C1021V 64K x 16 Static RAM Features Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is	Original	cy7c1021v i/o16 cy7c1021v33-12zc cy7c1021v33-15zi +2cy7c1021v33-10vc cy7c1021v33-10zc	PDF
EPM5128LC Abstract: IDT CYPRESS CROSS REFERENCE clocks epm5064lc-1 EPM5128LC-1 EPM5064LC EPM5128LC-2 EPM5128GI EPM5128JC-1 8464c 5962-8871309 Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2148-35C CY21L48-35C CY7C168A-35C CY7C168A-25C 5962-8871309XX 5962-89839112X CY2148-35C CY7C148-35C CY7C168A-45M CY7C168A-35M+ 5962-8871310RX 5962-8983913RX CY2148-35M CY7C148-35M CY7C169A-35C	Original	cy2148-35c cy21l48-35c cy7c168a-35c cy7c168a-25c +155962-8871309xx 5962-89839112x cy7c148-35c cy7c168a-45m cy7c168a-35m epm5128lc idt cypress cross reference clocks epm5064lc-1 epm5128lc-1 epm5064lc epm5128lc-2 epm5128gi epm5128jc-1 8464c 5962-8871309	PDF
Contextual Info: 1I S 8 K J F P 7C1021 YJl xP 1 RiXJjEkw/i^ F ^ _ — 64K x 16 Static RAM BLE is LOW, then data from I/O pins (l/0 1 through l/0 8), is written into the location specified on the address pins (A0 through A i5). If byte high enable (BHE) is LOW, then data from	OCR Scan	cy7c1021	PDF
15BAI Contextual Info: 33 7C1021BV33 PRELIMINARY 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable CE and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 1 through I/O8), is written into the location specified on the address pins (A0	Original	cy7c1021bv33 44-pin 400-mil 48-ball +115bai	PDF
7C1021B-15 Abstract: 10211B CY7C1021B-12VC CY7C10211B CY7C1021B Contextual Info: 0211B 7C1021B/ 7C10211B 64K x 16 Static RAM Features • High speed — tAA = 10, 12, 15 ns • CMOS for optimum speed/power • Low active power — 825 mW max. • Automatic power-down when deselected • Independent control of upper and lower bits	Original	0211b cy7c1021b/cy7c10211b 44-pin +6400-mil cy7c1021b/10211b cy7c1021b 7c1021b-15 10211b cy7c1021b-12vc	PDF
CY7C10211B Abstract: CY7C1021B Contextual Info: 7C1021B 7C10211B 1-Mbit 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0	Original	cy7c1021b cy7c10211b i/o16 cy7c1021b/cy7c10211b	PDF
CY7C1021B Abstract: CY7C1021B-10VC Contextual Info: 7C1021B 7C1021B 64K x 16 Static RAM Features BLE is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location	Original	1cy7c1021b cy7c1021b i/o16 44-pin +2400-mil cy7c1021b-10vc	PDF
A12C Abstract: A14C A15C CY7C1021V Contextual Info: fax id: 1077 C Y7C 1021V 64K x 16 Static RAM Features Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (l/O-i through l/Og), is written into the location specified on the address pins (Aq	OCR Scan	44-pin 400-mil cy7c1021v a12c +2a14c a15c	PDF
verilog for SRAM 512k word 16bit Abstract: CY62512V CYM74P436 192-Macrocell 62128 sram 7C1350 Triton P54C palce16v8 programming guide 7C168A intel 16k 8bit RAM chip Contextual Info: Product Selector Guide Static RAMs Organization/Density Density X1 X4 4K X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 16K 7C167A 7C168A 7C128A 6116 64K to 72K 7C187 7C164 7C166 7C185 6264 7C182 256K to 288K 7C197 7C194 7C195 7C199 7C1399/V 62256/V 62256V25 62256V18	Original	7c148 7c149 7c150 7c167a +157c168a 7c128a 7c187 7c164 7c166 7c185 verilog for sram 512k word 16bit cy62512v cym74p436 192-macrocell 62128 sram 7c1350 triton p54c palce16v8 programming guide intel 16k 8bit ram chip	PDF
A13L Abstract: CY7C1021V Contextual Info: 7C1021V V CYPRESS 64K x 16 Static RAM Features W riting to th e device is a c c o m plished by takin g chip ena b le CE and w rite enable (W E) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (l/O-i throu gh l/O g ), is w ritten into the location sp e cified on the address pins (A0	OCR Scan	cy7c1021v 44-pin 400-mil 48-ball +1a13l	PDF

7C1021 Search Results

7C1021 Price and Stock

Infineon Technologies AG CY7C1021D-10ZSXI

Infineon Technologies AG CY7C1021D-10VXI

Infineon Technologies AG CY7C1021DV33-10VXI

Infineon Technologies AG CY7C1021D-10ZSXIT

Vishay Intertechnologies RNR57C1021FSBSL1

7C1021 Datasheets Context Search

550mi

CY7C1021

7C1021

ATPA

CY7C1021BN-15VI

CY7C1021BN

CY7C1021V30

CY7C1021BV

CY7C1021B-15ZSXE

CY7C1021V33-15VI

7C1021-10

CY7C1021V33-12ZC

EPM5128LC

15BAI

7C1021B-15

CY7C10211B

CY7C1021B

A12C

verilog for SRAM 512k word 16bit

A13L