A13L Search Results

Contextual Info: A13LL71 V rsm V rrm Vdrm V 500 700 900 1100 1300 V 400 600 800 1000 1200 1500 1700 1400 1600 V/ JS 500 500 500 500 500 1000 1000 1000 Sin. It s m Tvj 180; (Tease = • • • Tvj = = = = tgd Tvj = 25 °C; tgr Vd T Vj i2t T vj 25 °C; 130 °C; 25 °C; 130 °C;

9l reset

Abstract: CY7C0852V-133AC CY7C09289V CY7C09369V CY7C09379V
Contextual Info: CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features Functional Description

IDT709079

Abstract: IDT709089
Contextual Info: 025/0251 CY7C09079/89/99 CY7C09179/89/99 PRELIMINARY 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices — 32K x 8/9 organizations CY7C09079/179

A12L

Abstract: A13L CY7C09159V CY7C09169V
Contextual Info: fax id: 5208 CYPRESS CY7C09159V CY7C09169V PRELIMINARY 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM • H ig h-speed clo ck to d ata ac ce ss 7.5/12 ns m ax. Features • 3.3V Low o p e ratin g p ow er • True D u al-P o rted m e m o ry cells w h ich allo w sim u lta­

IDT709269

Abstract: IDT709279 014L 100-PIN
Contextual Info: fax id: 5217 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY ^ C Y P R E S S ~ 16K/32K/64K x16/18 Synchronous Dual Port Static RAM Features Low o p e ratin g p ow er • True D u al-P o rted m e m o ry cells w h ich allo w sim u lta­ n eo us ac c e s s o f th e s a m e m e m o ry location

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Abstract: TNC 24 mk 2 026R CY7C09569V tb136 A14L CY7C09579V
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -• -■ -■ -^ jjÉBT *¿f5’00“’ '*'^ 7“T ■ ■ ■ ■ <1; .r {• o CY7C09569V CY7C09579V PRELIMINARY f:,ò b 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM • 3.3V Low o p e ratin g p ow er

A15LC

Abstract: A14L A14LC A12LC CY7C09099V 751V
Contextual Info: “ tv * I PRELIMINARY CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow sim ulta­ neous access of the same memory location • 6 Flow-Through/Pipelined devices

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Contextual Info: HIGH-SPEED 32K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT709279S/L I n t e g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: Full synchronous operation on both ports - 4ns setup to clock and 1 ns hold on all control, data, and address inputs

Contextual Info: dt | ; HIGH-SPEED 16Kx 8 DUAL-PORT STATIC RAM IDT7006S/L In te g ra te d De v ic e T e ch n o lo g y, Inc. FEATURES: • • • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location • H igh-speed access — M ilitary: 20/25/35/55/70ns max.)

Contextual Info: HIGH-SPEED 16Kx 8 DUAL-PORT STATIC RAM IDT7006S/L Integrated Device Technology, Inc. M/S = L for BUSY input on Slave • Interrupt Flag • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

Contextual Info: PRELIMINARY IDT70V27S/L HIGH-SPEED 3.3V 32Kx 16 DUAL-PORT STATIC RAM In te g ra te d D e v iz e T e c h n o lo g y , l i e . FEATURES: • IDT70V27 easily expands data bus w idth to 32 bits or more using the M aster/Slave select when cascading more than one device

Contextual Info: HIGH-SPEED 32K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT709079S/L Integrated Device Technology, Inc. FEATURES: • • True Dual-Ported m em ory cells which allow sim ulta­ neous access of the sam e m em ory location • H igh-speed clock to data access

Contextual Info: Integrated D e v ile Technology, li e . HIGH-SPEED 3.3V 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS PRELIMINARY IDT70V7288S/L FEATURES: DESCRIPTION: • 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture — Four independent 16K x 16 banks

Contextual Info: HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM IDT7008S/L F eatu res * * * True Dual-Ported m em ory cells w hich allow sim ultaneous more u sin g the Master/Slave select when ca sca d in g more High-speed a c c e ss than one device_ - M ilitary: 25/35/55ns max.

Contextual Info: HIGH-SPEED 3.3V 32K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V9079S/L Features: additional logic Full synchronous operation on both ports True Dual-Ported memory cells which allow simultaneous access of the same memory location * High-speed clock to data access

Contextual Info: i|g; m I | • ''• d m r 1 M L HIGH-SPEED 3.3V 16K x 36 | SYNCHRONOUS PIPELINED DUAL-PORT STATIC ra m PRELIMINARY IDT70V3569S F ea tu re s: ♦ True Dual-Ported memory cells which allow simultaneous access of the same memory location ♦ High-speed clock to data access

Contextual Info: 1»ill 1IFV1F 1 1 U 1 ‘! S y P r • W 0 L HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V3569S F ea tu re s: ♦ True Dual-Ported memory cells which allow simultaneous access of the same memory location ♦ High-speed clock to data access

Contextual Info: HIGH-SPEED 3.3V 16Kx 16 DUAL-PORT STATIC RAM PRELIMINARY IDT70V26S/L Integrated Device Technology, Inc. • FEATURES: • • • • • True Dual-Ported m em ory cells which allow sim ulta­ neous reads of the same m em ory location High-speed access — Com mercial: 25/35/55ns max.

Contextual Info: PRELIMINARY IDT70V27S/L HIGH-SPEED 3.3V 3 2Kx 16 DUAL-PORT STATIC RAM In te g ra te d D e vice T e ch n o lo g y, Inc. FEATURES: • • True Dual-Ported memory cells which allow simulta­ neous access of the same memory location • High-speed access — Commercial: 25/35/55ns max.

Contextual Info: PRELIMINARY IDT709089S/L HIGH-SPEED 64K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Integrated Device Technology, Inc. FEATURES: • • • • • • • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location

7M135

Contextual Info: CMOS DUAL-PORT RAM MODULE 64K 8K x 8-BIT & 128K (16Kx 8-BIT) FEATURES: • H ig h -d e n sity 6 4 K /1 28 K -b it C M O S d u a l-p o rt RAM m o du le s • 16K x 8 o rg a n iza tio n (ID T7M 135) w ith 8K x 8 o p tio n (IDT7M 134) • Low p o w e r co n su m p tio n

Contextual Info: HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L I n t e g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: more using the M aster/Slave select when cascading more than one d evice • M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave

Contextual Info: HIGH-SPEED 1 6 K X 9 DUAL-PORT STATIC RAM ID T 7 0 1 6 S /L Features using the Master/Slave select when cascading more than * True Dual-Ported memory cells which allow sim ultaneous one d e v i c e _ reads of the sam e memory location M/S = V ih for B U S Y output flag on Master

Contextual Info: HIGH-SPEED 3.3V 64K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V9089S/L In te g ra te d D e v iz e T e c h n o lo g y , l i e . FEATURES: • • • • • • • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location