7C101 Search Results

Contextual Info: 7C101A: 11-25-91 Revision: Thursday, February 18,1993 7C101A CY7C102A k ' Vwt S3 « 3 PRELIMINARY 7J= CYPRESS SEMICONDUCTOR 256K x 4 Static RAM with Separate I/O Features Functional Description • Highspeed — tAA = 12 ns • Transparent write 7C101A

CY7C102-35PC

Abstract: 7C101-35 HO- 21C L7535 2C1012
Contextual Info: CYPRESS SE MI CO NDU CTOR MbE D B 250^5 GOObSflö □ E3CYP 'T - ^ - V b A O ,V ilT ' '-• * •' * ' CYPRESS SEMICONDUCTOR 262,144 x 4 Static RfW RAM with Separate I/O Features Functional Description • H ighspeed — tAA = 25 ns • Ttgnsparent write (7C101

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR Functional Description • High speed T he C Y 7C101A and CY 7C102A are highperform ance C M O S static R A M s orga­ nized as 262,144 x 4 bits with separate I/O. Easy m em ory expansion is provided by ac­ tive LO W chip enable C E and threestate drivers. B oth devices have an a u to ­

Contextual Info: 7C101A CY7C102A PRELIMINARY CYPRESS SEMICONDUCTOR Features Functional Description • High speed T he C Y 7C101A and CY 7C102A are highp erform ance C M O S static R A M s orga­ nized as 262,144 x 4 bits w ith separate I/O . Easy m em ory expansion is provided by ac­

CY7C101A

Abstract: CY7C102A 7C101A-12 l3lx
Contextual Info: PRELIMINARY 9 / C Y PR E SS 7C101A CY7C102A 256K x 4 Static RAM with Separate I/O Features Functional Description • High speed The 7C101A and CY7C102A are high­ perform ance CMOS static RAM s orga­ nized as 262,144 x 4 bits with separate I/O. Easy m emory expansion is p rovided by ac­

CY7C1014

Contextual Info: V CYPRESS Features • H igh speed — U a = 10 n s • C M O S for optim um speed/pow er • C enter power/ground pinout • A utom atic power-down w hen deselected • TT L -com patible in p u ts and outputs Functional Description The 7C1014 is a high-perform ance

transistor c1016

Abstract: c1016 CY7C1016 C10161
Contextual Info: fax id: 1057 1CY 7C10 16 ADVANCED INFORMATION 7C1016 256K x 4 Static RAM Features output enable OE , and three-state drivers. The device has an automatic power-down feature that significantly reduces power consumption when deselected. • High speed — tAA = 10 ns

Scans-051

Contextual Info: fax id: 1050 C Y7C 1019 128Kx 8 Static RAM — tAA = 1 0 ns Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. Data on the eight I/O pins (l/O0 through l/0 7) is then written into the location speci­ fied on the address pins (A0 through A 16).

CY7C1019

Contextual Info: 1CY 7C10 19 ADVANCED INFORMATION 7C1019 128K x 8 Static RAM Features • High speed — tAA = 10 ns • CMOS for optimum speed/power • Center power/ground pinout • Automatic power-down when deselected • Easy memory expansion with CE and OE options

ATPA

Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C

7C241

Abstract: 7c471 7C121 7C820K 7C221 7C390K 6861K 90K110 5C56 12C-390K
Contextual Info: METAL OXIDE VARISTORS TNR Chip Type For Direct Surface Mounting 5C and 7C Type ?RATINGS Operating Temperature Range: -40K+125C Storage Temperature Range: -50K+150C Maximum Applied Voltage (Continuous) AC. (Vrms) DC. (V) 18 14 22 17 26 20 30 25 37 30 44

Contextual Info: 7C1019D PRELIMINARY 1-Mbit 128K x 8 Static RAM Functional Description[1] Features • Pin- and function-compatible with 7C1019B • High speed — tAA = 10 ns • CMOS for optimum speed/power • Low active power The 7C1019D is a high-performance CMOS static RAM

CY7C1018

Abstract: CY7C1018DV33
Contextual Info: PRELIMINARY 7C1018DV33 1-Mbit 128K x 8 Static RAM Functional Description[1] Features • Pin- and function-compatible with 7C1018CV33 • High speed — tAA = 8 ns • Low Active Power — Icc = 75 mA @ 8 ns • Low CMOS Standby Power The 7C1018DV33 is a high-performance CMOS static

CY7C1019B

Abstract: CY7C1019B-10VC CY7C1019B-12VC CY7C1019V33 7C1019B-15
Contextual Info: C1019V33 7C1019B 128K x 8 Static RAM Features • High speed — tAA = 10 ns • CMOS for optimum speed/power • Center power/ground pinout • Automatic power-down when deselected • Easy memory expansion with CE and OE options • Functionally equivalent to 7C1019V33

CY7C1019

Abstract: CY7C1019BN CY7C1019BN-12VC CY7C1019BN-12ZC CY7C1019BN-12ZXC CY7C1019BN-15VC
Contextual Info: 7C1019BN 128K x 8 Static RAM Features Functional Description • High speed The 7C1019BN is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE , an active LOW Output Enable (OE), and three-state drivers. This

CY7C1016

Abstract: A0231 A2429 C10161
Contextual Info: 7c1006: 11-25-91 Revision: April 10, 1995 ADVANCED INFORMATION CMOS static RAM organized as 262,144 words by 4 bits. Easy memory expansion is D provided by an active LOW chip enable Ċ CE , an active LOW output enable (OE), and threeĆstate drivers. The device has an

CY7C101A

Abstract: CY7C102A
Contextual Info: 7C101A PRELIMINARY Functional Description Features D D D D D D D The 7C101A and CY7C102A are highĆ performance CMOS static RAMs orgaĆ nized as 262,144 x 4 bits with separate I/O. Easy memory expansion is provided by acĆ tive LOW chip enable CE and threeĆ

CY7C1019

Abstract: CY7C1019-10VC CY7C1019-12VC CY7C1019L-10VC
Contextual Info: PRELIMINARY 7C1019 128K x 8 Static RAM Features Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).

CY7C1011

Contextual Info: PRELIMINARY 7C1011 128K x 16 Static RAM Features BLE is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16).

7C101

Contextual Info: 7C101A CY7C102A PRELIMINARY 256Kx 4 Static RAM with Separate I/O Features Functional Description • High speed The 7C101Aand CY7C102A are highperformance CMOS static RAMs orga­ nized as 262,144 x 4 bits with separate I/O. Easy memory expansion is provided by ac­

CY7C1011-20VC

Contextual Info: 7C1011 1 2 8 K x 1 6 Static RAM BLE is LOW, then data from I/O pins (l/O 0 through l/0 7), is written into the location specified on the address pins (A 0 through A 16). If byte high enable (BHE) is LOW, then data from I/O pins (l/ 0 8 through l/0 15) is written into the location speci­

EPM5128LC

Abstract: IDT CYPRESS CROSS REFERENCE clocks epm5064lc-1 EPM5128LC-1 EPM5064LC EPM5128LC-2 EPM5128GI EPM5128JC-1 8464c 5962-8871309
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2148-35C CY21L48-35C CY7C168A-35C CY7C168A-25C 5962-8871309XX 5962-89839112X CY2148-35C CY7C148-35C CY7C168A-45M CY7C168A-35M+ 5962-8871310RX 5962-8983913RX CY2148-35M CY7C148-35M CY7C169A-35C

Contextual Info: 7C1018V33 7C1019V33 CYPRESS 128K x 8 Static RAM pins l/O0 through l/0 7 is then written into the location speci­ fied on the address pins (A q through A-ie)- Features • High speed Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write

*7C471

Abstract: 7c471 7C241 7C221 p03 varistor TNR Varistor TNR9C271K 9C33
Contextual Info: TNR C SERIES ◆ Taping Specification ● The Specifications for TNR C Series B W F E FD0 T FD1 A P1 P3 T2 A Size Code 5C-A 5C-B 7C 9C 12C B P0.1 6.9 6.85 8.3 10.85 12.5 P2 W P0.1 10.4 8.05 10.6 13.0 16.3 Direction of feed F E P0.3 P0.1 16.0 7.5 24.0 Dimensions mm