CY7C102 Search Results

CY7C1022

Contextual Info: Y7C10 PRELIMINARY CY7C1022 32K x 16 Static RAM Features • 5.0V operation ± 10% • High speed — tAA = 12 ns • Low active power — 825 mW (max., 10 ns, “L” version) • Very Low standby power — 500 µW (max., “L” version) • Automatic power-down when deselected

CY7C1020

Contextual Info: Y7C10 PRELIMINARY CY7C1020 32K x 16 Static RAM Features BLE is LOW, then data from I/O pins (I/O 1 through I/O8), is written into the location specified on the address pins (A0 through A 14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14).

A14C

Abstract: CY7C1022
Contextual Info: fax id: 1105 -mr ' : : .üÉÉÉÉÉÉÉÉÉÉüiüiüHjjju'.' •^M .-X^,. : : : IS . .: : : ' : ; : : : ; : CY7C1022 P R E L IM IN A R Y •rriM U M iM iiiu m m r :iÉÉ ¡Ígg^-'í^ : t V Kw^ :1- JÜ § « < !N : — I" | :|3 : k j k-D 32K Features

CY7C101A

Abstract: CY7C102A 7C101A-12 l3lx
Contextual Info: PRELIMINARY 9 / C Y PR E SS CY7C101A CY7C102A 256K x 4 Static RAM with Separate I/O Features Functional Description • High speed The CY7C101A and CY7C102A are high­ perform ance CMOS static RAM s orga­ nized as 262,144 x 4 bits with separate I/O. Easy m emory expansion is p rovided by ac­

A10C

Abstract: A14C CY7C1020
Contextual Info: fax id: 1074 PRELIMINARY CY7C1020 WO YPHESS 32K Features BLE is LOW, then da ta from I/O pins (l/O-i thro u g h l/Og), is w ritten into the location specified on the address pins (A 0 throu gh A 1 4 ). If byte high enable (BHE) is LOW, then da ta from I/O pins (l/Og throu gh l/O-ie) is w ritten into the location sp e ci­

7C1021

Abstract: C2223 ge639 A12C CY7C1021
Contextual Info: CYPRESS Features • 12 ns • C M O S for optim um speed/pow er • L ow active power — 1020 mW • A vailable in 450 x 550-m il LCC • A utom atic power-down w hen deselected • E asy m em ory exp an sion w ith C Ej, CE 2, and O E options CY7C1021 64K x 16 Static RAM

CY7C1021V30

Abstract: CY7C1021V30-15BAI
Contextual Info: CY7C1021V30 64K x 16 Static RAM Features W riting to the device is a cco m plished by takin g C hip Enable CE and W rite Enable (W E) inputs LOW. If Byte Low Enable (BLE) is LOW, then da ta from I/O pins (l/O-i throu gh l/Og), is w ritten into the location specified on th e address pins (A0

Contextual Info: fax id: 1075 CY7C1020V _ Features 32Kx 16 Static RAM BLE is LOW, then data from I/O pins (l/0-| through l/0 8), is written into the location specified on the address pins (Aq through A 1 4 ). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through l/0-|6) is written into the location speci­

Contextual Info: 7C101A: 11-25-91 Revision: Thursday, February 18,1993 CY7C101A CY7C102A k ' Vwt S3 « 3 PRELIMINARY 7J= CYPRESS SEMICONDUCTOR 256K x 4 Static RAM with Separate I/O Features Functional Description • Highspeed — tAA = 12 ns • Transparent write 7C101A

Contextual Info: PRELIMINARY CY7C1020 3 2 K x 16 Static RAM Features BLE is LOW, then data from I/O pins <l/0-| through l/0 8), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (l/09 through l/0 16) is written into the location speci­

CY7C1021BV33

Abstract: CY7C1021CV33 TSOP 48 thermal resistance
Contextual Info: CY7C1021CV33 1-Mbit 64K x 16 Static RAM Functional Description[1] Features • Temperature Ranges The CY7C1021CV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces

550mi

Contextual Info: 7c1021: March 31,1995 Revised: June 25,1996 CY7C1021 64K x 16 Static RAM ADVANCED INFORMATION Features Functional Description The CY7C1021 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW chip enable

Contextual Info: fax id: 1083 C 'i- PRELIMINARY CY7C1021V30 64K Features X 16 Static RAM Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BEE) is LOW, then data from I/O pins (l/Oi through l/0 8), is written into the location specified on the address pins (A0

Contextual Info: CY7C1021 P Yi. PX :V«*1 64K x 16 Static RAM BLE is LOW, then data from I/O pins (l/0-| through l/0 8), is written into the location specified on the address pins (A0 through A i5). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through I/0 1 6) is written into the location speci­

Contextual Info: CY7C1021BNV33 64 K x 16 Static RAM 64 K × 16 Static RAM Features Functional Description The CY7C1021BNV33[1] is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power

CY7C1021BN-15VI

Abstract: CY7C1021BN
Contextual Info: CY7C1021BN CY7C10211BN 1-Mbit 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0

CY7C1024DV33

Contextual Info: CY7C1024DV33 PRELIMINARY 3-Mbit 128K X 24 Static RAM Features Functional Description • High speed The CY7C1024DV33 is a high-performance CMOS static RAM organized as 128K words by 24 bits. This device has an automatic power-down feature that significantly reduces

CY7C1020B

Contextual Info: 020B CY7C1020B 32K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable CE and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0

CY7C1021BN

Contextual Info: CY7C1021BN CY7C10211BN 1-Mbit 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0

CY7C1020CV33

Abstract: CY7C1020V33
Contextual Info: CY7C1020CV33 512K 32K x 16 Static RAM Features Functional Description • Pin- and function-compatible with CY7C1020V33 • Temperature Ranges — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C The CY7C1020CV33 is a high-performance CMOS static

CY7C1021CV33

Abstract: CY7C1021DV33 CY7C1021DV33-10VXI
Contextual Info: CY7C1021DV33 1-Mbit 64K x 16 Static RAM Functional Description[1] Features • Temperature Ranges The CY7C1021DV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces

CY7C1024AV33

Contextual Info: 024AV33 CY7C1024AV33 128K x 24 Static RAM Features Writing to the device is accomplished by taking Chip Enable CE1, CE2, CE3 active and Write Enable (WE) inputs LOW. Data on the 24 I/O pins (I/O0 through I/O23) is then written into the location specified on the address pins (A0 through A16).

A14C

Abstract: CY7C1020V
Contextual Info: fax id: 1075 ^ ;a a a z g g s t CY7C1020V PRELIMINARY ; U I F lm ß b ö 32K Features 16 Static RAM X BLE is LOW, then da ta from I/O pins (l/O-j throu gh l/ 0 8), is w ritten into the location specified on th e address pins (A 0 throu gh A-| 4 ). If byte high en ab le (BH E) is LOW, then da ta from

Contextual Info: CY7C1021D PRELIMINARY 1-Mbit 64K x 16 Static RAM Features automatic power-down feature that significantly reduces power consumption when deselected. • Pin- and function-compatible with CY7C1021B • High speed — tAA = 10 ns • CMOS for optimum speed/power