BG119 Search Results

BG256

Abstract: BG352 352-LEAD
Contextual Info: Package Diagrams Ball Grid Array Packages 119-Lead FBGA 14 x 22 x 2.4 mm BG119 51-85115 1 Package Diagrams 256-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG256 51-85097 2 Package Diagrams 352-Lead Ball Grid Array (35 x 35 x 2.33 mm) BG352 51-85103 3

Diagrams

Abstract: 5185143 BG-272 mold cap BG256 BG352 BG-209 Package Diagrams 14X22
Contextual Info: Package Diagrams Ball Grid Array Packages 119-Lead PBGA 14 x 22 x 2.4 mm BG119 51-85115-*A 1 Package Diagrams 209-Lead PBGA (14 x 22 x 2.20 mm) BG209 51-85143-*A 2 Package Diagrams 256-Lead PBGA (27 x 27 x 2.33 mm) BG256 51-85097-*A 3 Package Diagrams 272-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG272

BG-272

Abstract: 5185130
Contextual Info: Package Diagrams Ball Grid Array Packages 119-Lead FBGA 14 x 22 x 2.4 mm BG119 51-85115 1 Package Diagrams 256-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG256 51-85097 2 Package Diagrams 272-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG272 51-85130 3 Package Diagrams

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

DSC5002

Contextual Info: 256K x 36, 512K x 18 2.5V Synchronous ZBTTM SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Features u 256K x 36, 512K x 18 memory configurations u Supports high performance system speed - 200 MHz Address and control signals are applied to the SRAM during one

IDT71V3576

Abstract: IDT71V3578
Contextual Info: 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Preliminary IDT71V3576 IDT71V3578 Description 128K x 36, 256K x 18 memory configurations Supports high system speed:

IDT71V2556

Abstract: IDT71V2558
Contextual Info: 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Preliminary IDT71V2556 IDT71V2558 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ cycle, and two cycles later the associated data cycle occurs, be it read

Contextual Info: 256K x 36, 512K x 18 2.5V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Preliminary IDT71T65702 IDT71T65902 it read or write. The IDT71T65702/5902 contain address, data-in and control signal

IDT71V67602

Abstract: IDT71V67802
Contextual Info: 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Advance Information IDT71V67602 IDT71V67802 256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,

IDT71T67702

Abstract: IDT71T67902
Contextual Info: 256K X 36, 512K X 18 Advance 2.5V Synchronous SRAMs Information 2.5V I/O, Burst Counter IDT71T67702 Flow-Through Outputs, Single Cycle Deselect IDT71T67902 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ data, address and control registers. There are no registers in the data

Contextual Info: CY7C1361A CY7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0ns Fast clock speed: 150, 133, 117, and 100MHz Fast OE access times: 3.5 ns and 4.0 ns

71V2578

Contextual Info: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V2576S IDT71V2578S IDT71V2576SA IDT71V2578SA Description 128K x 36, 256K x 18 memory configurations

CY7C1386C

Abstract: CY7C1387C
Contextual Info: CY7C1386C CY7C1387C 18-Mb 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

A23 1101 01A

Contextual Info: 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V3557S IDT71V3559S IDT71V3557SA IDT71V3559SA it read or write. The IDT71V3557/59 contain address, data-in and control signal

CY7C1360C-250BGC

Abstract: CY7C1360C CY7C1362C CY7C1360C-166BZI
Contextual Info: CY7C1360C CY7C1362C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz

IDT71V25761

Abstract: IDT71V25781 71V25761 71V2578
Contextual Info: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V25761 IDT71V25781 Description 128K x 36, 256K x 18 memory configurations Supports high system speed:

CY7C1325G

Abstract: CY7C1325G-133AXC CY7C1325G-133AXI CY7C1325G-133BGC CY7C1325G-133BGI CY7C1325G-133BGXC CY7C1325G-133BGXI
Contextual Info: CY7C1325G PRELIMINARY 4-Mbit 256K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 256K X 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version)

IDT71V65702

Abstract: IDT71V65902
Contextual Info: 256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs Preliminary IDT71V65702 IDT71V65902 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36, 512K x 18 memory configurations Supports high performance system speed - 100 MHz

CY7C1327B

Contextual Info: 327 CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM Features The CY7C1327B I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

CY7C1381B-100AI

Abstract: 381B CY7C1381B CY7C1381B-117AC CY7C1383B
Contextual Info: 381B CY7C1381B CY7C1383B 512 x 36/1M × 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 10.0 ns Fast clock speed: 117, 100, 83 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion

80486 microprocessor block diagram and pin diagram

Abstract: CY7C1338B
Contextual Info: 338B CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence

CY7C1327G

Abstract: CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI
Contextual Info: CY7C1327G PRELIMINARY 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times

GVT71256ZC36B-7.5

Abstract: CY7C1356A-100AC CY7C1356A GVT71512ZC18
Contextual Info: PRELIMINARY CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 166, 133, and 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns

CY7C1381A

Abstract: CY7C1381A-100AC CY7C1381A-117AC CY7C1381A-83AC
Contextual Info: CY7C1381A CY7C1383A PRELIMINARY 512K x 36 / 1M x 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 9.0, 10.0 ns Fast clock speed: 117, 100, 83, 66 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion