5185143 Search Results

CY7C1461V25

Abstract: CY7C1463V25 CY7C1465V25
Contextual Info: CY7C1461V25 CY7C1463V25 CY7C1465V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles •Supports 133-MHz bus operations •1M x 36/2M × 18/512K × 72 common I/O

Contextual Info: CY7C1480V33 CY7C1482V33 CY7C1486V33 ADVANCE INFORMATION 2M x 36/4M x 18/1M x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 300, 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate

CY7C1440V33

Contextual Info: CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.7, 3.0 and 3.5 ns

cy7c1470v25

Contextual Info: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Contextual Info: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Functional Description Features The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are

Contextual Info: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Contextual Info: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT

250ac to 30 v ac

Abstract: CY7C1462V25 CY7C1464V25 CY7C1460V25
Contextual Info: CY7C1460V25 CY7C1462V25 CY7C1464V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns

CY7C1443V33

Abstract: CY7C1441V33
Contextual Info: CY7C1441V33 CY7C1443V33 CY7C1447V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-through SRAM Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • Fast clock-to-output times — 6.5 ns for 133-MHz device — 7.5 ns (for 117-MHz device)

cy7c147bv-25

Contextual Info: CY7C1471V25 72-Mbit 2 M x 36 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

Contextual Info: CY7C1441AV33 36-Mbit 1 M x 36 Flow-Through SRAM 36-Mbit (1 M × 36) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times

cy7c1470v25

Contextual Info: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Diagrams

Abstract: 5185143 BG-272 mold cap BG256 BG352 BG-209 Package Diagrams 14X22
Contextual Info: Package Diagrams Ball Grid Array Packages 119-Lead PBGA 14 x 22 x 2.4 mm BG119 51-85115-*A 1 Package Diagrams 209-Lead PBGA (14 x 22 x 2.20 mm) BG209 51-85143-*A 2 Package Diagrams 256-Lead PBGA (27 x 27 x 2.33 mm) BG256 51-85097-*A 3 Package Diagrams 272-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG272

CY7C1441V33

Abstract: CY7C1443V33
Contextual Info: CY7C1441V33 CY7C1443V33 CY7C1447V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM Features inputs include all addresses, all data inputs, addresspipelining Chip Enable CE , Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd,

Contextual Info: CY7C1471V33 72-Mbit 2 M x 36 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Functional Description Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

cy7c1470v25

Contextual Info: CY7C1470V25 CY7C1472V25 CY7C1474V25 ADVANCE INFORMATION 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between Write and Read cycles • Fast clock speed: 300, 250, 200, and 167 MHz • Fast access time: 2.2, 2.4, 3.0, and 3.4 ns

Contextual Info: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT

CY7C1470V25

Abstract: CY7C1472V25 CY7C1474V25
Contextual Info: CY7C1470V25 CY7C1472V25 CY7C1474V25 PRELIMINARY 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between Write and Read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.6, 3.0, and 3.4 ns

CY7C1460V33

Abstract: CY7C1462V33
Contextual Info: CY7C1460V33 CY7C1462V33 CY7C1464V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns

CY7C1461V25

Abstract: CY7C1463V25 CY7C1465V25
Contextual Info: CY7C1461V25 CY7C1463V25 CY7C1465V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 F/T SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles •Supports 133-MHz bus operations •1M x 36/2M x18/512K x 72 common I/O

tdb 117

Abstract: CY7C1471V33 CY7C1473V33 CY7C1475V33
Contextual Info: CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY 2M x 36/4M x 18/1M x 72 Flow-through SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Supports 133-MHz bus operations • 2M x 36/4M × 18/1M × 72 common I/O

Contextual Info: CY7C1441AV33 36-Mbit 1 M x 36 Flow-Through SRAM 36-Mbit (1 M × 36) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times

CY7C1481V33

Abstract: CY7C1483V33 CY7C1487V33
Contextual Info: CY7C1481V33 CY7C1483V33 CY7C1487V33 PRELIMINARY Logic Block Diagrams CY7C1481V33 – 2M x 36 MODE A[1;0] 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP Q A[20:0] 21 GW 19 DQd, DPd BYTEWRITE REGISTERS DQc, DPc BYTEWRITE REGISTERS Q D DQb, DPb BYTEWRITE REGISTERS

Contextual Info: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Functional Description Features • Pin-compatible and functionally equivalent to ZBT™