CY7C1383A Search Results

CY7C1381A

Abstract: CY7C1381A-100AC CY7C1381A-117AC CY7C1381A-83AC
Contextual Info: CY7C1381A CY7C1383A PRELIMINARY 512K x 36 / 1M x 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 9.0, 10.0 ns Fast clock speed: 117, 100, 83, 66 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion

CY7C1381A

Contextual Info: CY7C1381AV25 CY7C1383AV25 PRELIMINARY 512K x 36 / 1M x 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 9.0, 10.0 ns Fast clock speed: 117, 100, 83, 66 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion

CY7C1381B

Abstract: CY7C1381BV25 CY7C1383B CY7C1383BV25
Contextual Info: CY7C1381BV25 CY7C1383BV25 PRELIMINARY 512K x 36 / 1M x 18 Flow-Thru SRAM Features controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), Burst Control Inputs

CY7C1381B

Abstract: CY7C1381BV25 CY7C1383B CY7C1383BV25
Contextual Info: CY7C1383BV25 CY7C1381BV25 512K x 36 / 1M x 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 10 ns Fast clock speed: 117, 100, 83 MHz Provide high-performance 2-1-1-1 access rate Optimal for depth expansion

Contextual Info: 1CY7C1381B CY7C1381B CY7C1383B PRELIMINARY 512K x 36 / 1 Mb x 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 6.5, 7.5, 8.5 ns Fast clock speed: 133, 117, 100 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion

CY7C1381B

Abstract: CY7C1381BV25 CY7C1383B CY7C1383BV25
Contextual Info: CY7C1383BV25 CY7C1381BV25 512K x 36 / 1M x 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 10 ns Fast clock speed: 117, 100, 83 MHz Provide high-performance 2-1-1-1 access rate Optimal for depth expansion

CY7C1338-100AXC

Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
Contextual Info: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12

EPM5128LC

Abstract: EPM5128GC epm5064lc-1 EPM5128LC1 59628867809r 5962-8984106LX EPM5128GI 7C19945DMB EPM5130GC-1 5962-8867812rx
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 5962-8753903LX 5962-8753902LX CY21L49-55C CY21L49-45C CY7C281 CY7C281A 5962-8863701LX 5962-8753902LX CY6116A-45C CY6116A-35C CY7C286 CY27H512 5962-8867003LX 5962-8867002LX CY6116A-55C CY6116A-45C

381B

Abstract: CY7C1381B CY7C1383B CY7C1381B-100AC
Contextual Info: 381B CY7C1381B CY7C1383B PRELIMINARY 512K x 36 / 1M x 18 Flowthrough SRAM Features • • • • • • • • • • • Fast access times: 6.5, 7.5, 8.5 ns Fast clock speed: 133, 117, 100 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion

CY7C1381B

Abstract: CY7C1381BV25 CY7C1383B CY7C1383BV25
Contextual Info: 1 CY7C1381BV25 CY7C1383BV25 PRELIMINARY 512K x 36 / 1 Mb x 18 Flow-Thru SRAM Features burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc,