A10C Search Results

A10C

Contextual Info: C orporate Hom e | Electronic Components | Se gm e nts | W ho W e Are My Account Searc h Products Documentation Resources My Account Customer Support Home > Products > By Type > Pin & Socket C onnectors > Product Feature Selector > Product Details M83513/04-A10C Product Details

A10C

Contextual Info: C orporate Hom e | Electronic Components | Se gm e nts | W ho W e Are My Account Searc h Products Documentation Resources My Account Customer Support Home > Products > By Type > Pin & Socket C onnectors > Product Feature Selector > Product Details M83513/03-A10C Product Details

Contextual Info: PRELIMINARY 4,194,304 WORD x 1 BIT DYNAMIC RAM DESCRIPTION The TC514101AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TC514101AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as advanced circuit techniques to provide wide operating m argins, both internally and to the system user.

Contextual Info: TMS44100, TMS44100P 4194304-BIT DYNAMIC RANDOM-ACCESS MEMORY SMHS410F-SEPTEMBER 1989-REVISED DECEMBER 1992 Single 5-V Power Supply ±10% Tolerance Performance Ranges: ACCESS ACCESS ACCESS SD P AC K A G E t (TOP VIEW) DJ P A C K A G E t (TOP VIEW) Organization . . . 4194 304 x 1

A100COLUMN

Contextual Info: 4 ,1 9 4 ,3 0 4 W ORD x 1 BIT D Y N A M IC R A M * This is advanced information and specifica­ tions are subject to change without notice. DESCRIPTION The TC514101AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TC514101AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as

tc5117400f

Abstract: TC5117400J
Contextual Info: TOSHIBA TC5117400J/Z/FT-60/70 4,194,304 WORD X 4 BIT DYNAMIC RAM DESCRIPTION The TC5117400J/Z/FT-60/70 is the new generation dynamic RAM organized 4,194,304 word by 4 bit. The TC5117400J/Z/FT-60/70 utilizes Toshiba’s CMOS silicon gate process technology as well as advanced

TYCO electronics marking code date

Abstract: A05C
Contextual Info: 4 T H IS D R A W IN G IS 3 U N P U B L IS H E D . R ELEASED FO R ALL C O P Y R IG H T B Y 1T C O E L E C T R O N IC S -, - P U B L IC A T IO N IN TE R N A TIO N A L RIGHTS 2 REVIS IO N S R E S E R VE D . C O R P O R A T IO N . D E S C R IP T IO N PR O D U C T IO N

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A - AUGUST 1995 - REVISED APRIL 1998 • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • Output-Ready and Almost-Empty Flags Synchronized by CLKB • Clocked FIFO Buffering Data From Port A

Using the TMS320C674x BootLoader

Contextual Info: TMS320C6743 SPRS565B – APRIL 2009 – REVISED JUNE 2011 www.ti.com TMS320C6743 Fixed/Floating-Point Digital Signal Processor Check for Samples: TMS320C6743 1 TMS320C6743 Fixed/Floating-Point Digital Signal Processor 1.1 Features 12 • Highlights – Up to 375-MHz FIxed/Floating-Point VLIW

BR17

Contextual Info: TMS320C6474 SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com TMS320C6474 Multicore Digital Signal Processor 1 Features 12 • Key Features – High-Performance Multicore DSP C6474 – Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns

Contextual Info: SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual JANUARY 2008 SPRS462B SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual Literature Number: SPRS462B SEPTEMBER 2007 – Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date.

514405BJ

Contextual Info: 1M x 4-Bit Dynamic RAM Hyper Page Mode (EDO version) HYB 514405BJ/BJL-50/-60/-70 Preliminary Information • 1 048 576 words by 4-bit organization • 0 to 70 ˚C operating temperature • Hyper Page Mode - EDO • Performance: -50 -60 -70 tRAC RAS access time

a13c

Abstract: 7C166 CY7C164 CY7C166 7C166-20 CY7C164-12VC 7C164-12 7C164 CY7C164-20PC
Contextual Info: CY7C164 CY7C166 m 'w CYPRESS 16K x 4 Static RAM Features Functional Description • High speed — 15 ns T he CY7C164 and CY7C166 are high-per­ form ance CMOS static RAM s organized as 16,384 by 4 bits. Easy mem ory expan­ sion is provided by an active LO W chip en­

K73 Package

Abstract: 3 phase inverter schematic diagram 7C166 CY7C164A CY7C166A CI64A CY7C164A-45DMB
Contextual Info: 4bE D CYPRESS SEM IC ON DU CT OR □ - p q & eSÛ'IbbE OQObMfiS 2 R3CYP .r S - l O C Y 7 C I6 4 A C Y 7 C 1 6 6 A ";ui'./^CTPRESS , _ SEMICONDUCTOR 16,384 x 4 Static R/W RAM Features Functional Description • Automatic power-down when

Contextual Info: TMS320C6746 SPRS591C – NOVEMBER 2009 – REVISED OCTOBER 2011 www.ti.com TMS320C6746 Fixed/Floating-Point DSP Check for Samples: TMS320C6746 1 TMS320C6746 Fixed/Floating-Point DSP 1.1 Features 12 • Highlights – 375/456-MHz C674x Fixed/Floating-Point

7813 Texas Instruments Transistor

Abstract: TMS320C6000 TMS320C6474 C6000 C6474 C64X DDR2-667 SPRS552H BR17
Contextual Info: TMS320C6474 SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com TMS320C6474 Multicore Digital Signal Processor 1 Features 12 • Key Features – High-Performance Multicore DSP C6474 – Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns

AM29F100T

Contextual Info: HNA: AMDB Am29F100 1 Megabit 128 K x 8-bit/64 K x 16-bit CMOS 5.0 Volt-only, Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS • Single power supply operation — 5.0 V + 10% for read, erase, and program operations — Simplifies system-level power requirements

Contextual Info: TMS320C6454 Fixed-Point Digital Signal Processor SPRS311C – APRIL 2006 – REVISED MAY 2007 1 Features • • • • • • High-Performance Fixed-Point DSP C6454 – 1.39-, 1.17, and 1-ns Instruction Cycle Time – 720-MHz, 850-MHz, and 1-GHz Clock Rate

Contextual Info: TMS320C6455 Fixed-Point Digital Signal Processor www.ti.com SPRS276F – MAY 2005 – REVISED MARCH 2007 1 TMS320C6455 Fixed-Point Digital Signal Processor 1.1 Features • • • • • • • High-Performance Fixed-Point DSP C6455 – 1.39-, 1.17 and 1-ns Instruction Cycle Time

arinc 404

Abstract: F40C1 d32c2 arinc size 8 coax contact 32F2
Contextual Info: DPX ARINC 404 DPX*MA/ME Contact Arrangement Variations, Crimp Type - DPX*M A/M E Series Rack and Panel Connectors N O T E : S e e p a g e s 5 8 - 6 1 fo r C o a x ia l C o n ta c t d a ta / .• • • •. \ • • • • No. of Contacts & Wire Size • • X

Contextual Info: TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com TMS320C6472 Fixed-Point Digital Signal Processor 1 Features • • • • • • • • • • • Congestion Control • IEEE 1149.6 Compliant I/Os – UTOPIA • UTOPIA Level 2 Slave ATM Controller

Contextual Info: TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 1 TMS320DM6437 Digital Media Processor 1.1 Features • • • • High-Performance Digital Media Processor DM6437 – 2.5-, 2.-, 1.67-, 1.51-, 1.43-ns Instruction

A00C

Contextual Info: TMS320C6454 Fixed-Point Digital Signal Processor SPRS311D – APRIL 2006 – REVISED OCTOBER 2007 1 Features • • • • • • High-Performance Fixed-Point DSP C6454 – 1.39-, 1.17, and 1-ns Instruction Cycle Time – 720-MHz, 850-MHz, and 1-GHz Clock Rate

transistor d880

Abstract: BR17
Contextual Info: TMS320C6474 www.ti.com SPRS552E – OCTOBER 2008 – REVISED APRIL 2010 TMS320C6474 Multicore Digital Signal Processor 1 Features 12 • Key Features – High-Performance Multicore DSP C6474 – Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns