54S11 Search Results

Contextual Info: LS73 LS76 LS107 LS112 Dual J-K Negative-Edge-Triggered Flip-Flops LS113 •Pin-for-Pin and functional equivalents to 5473, 5476, 54107, 54S112, 54S113 PIN-OUT DIAGRAMS DESCRIPTION These monolithic dual J-K flip-flops feature individual J, K, clock, and asynchronous preset and clear inputs to each

74S114

Abstract: ScansUX1001
Contextual Info: FAIRCHILD SUPER HIGH SPEED TTL/SSI . 9S114/54S114, 74S114 DUAL JK EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The 9S114/54S114, 74S114 o ffe r common clock and common clear inputs and individual J, K, and preset inputs. These m on o lith ic dual flip -flop s are designed so th a t when the clock goes HIG H , the inputs are enabled and data w ill be accepted. The logic

54S112

Abstract: totempole d2302
Contextual Info: Signetics 54S 112 Flip-Flop Dual J-K Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION The 54S112 is a dual J-K negative edge-triggered flip-flop featuring individu­ al J, K, Clock, Set and Reset inputs. The Set 5d and Reset (RD) inputs, when Low,

54ls10

Contextual Info: Signetics I 54LS10, 54S10, 54S11 Gates Triple Three-Input NAND ’10 , AND (’11) Gates Military Logic Products H FUNCTION TABLE ORDERING INFORMATION INPUTS Product Specification DESCRIPTION OUTPUTS A B C Y(’10) Y('11) L L L L H H H H L L H H L L H H L

SN54LS114A

Abstract: SN54S114 SN74 SN74LS114A SN74S114A LS114
Contextual Info: SN54LS114A, 54S114, SN74LS114A, SN74S114A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK MARCH 1973 —R EV ISED MARCH 1988 SN 54LS114A . SN 54S114 SN 74LS114A . SN 74S114A • Fully Buffered to Offer Maximum Isolation

74S112

Abstract: 54S112 ScansUX1001
Contextual Info: FAIRCHILD SUPER HIGH SPEED TTL/SSI • 9S112/54S112, 74S112 DUAL JK EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The 9S112/54S 112, 74S112 dual J K flip -flo p s feature individual J, K, clock, and asynchronous preset and clear inputs to each flip -flo p . When the clock goes H IG H , the inputs are enabled and data w ill be accepted. The logic level o f the J and K inputs may be

74S113

Abstract: ScansUX1001
Contextual Info: FAIRCHILD SUPER HIGH SPEED TTL/SSI • 9S113/54S113, 74S113 DUAL JK EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — T he 9 S 1 13 /5 4 S 1 13, 7 4 S 1 13 o ffe r in d iv id u a l J, K , preset, and c lo c k in p u ts. These m o n o lith ic dual flip -flo p s are designed so

LS107

Abstract: LS112 LS76 LS113 54S112 54S113 LS73 raytheon 74
Contextual Info: LS73 LS76 LS107 LS112 Dual J-K Negative-Edge-Triggered Flip-Flops _ LS113 •Pin-for-Pin and functional equivalents to 5473, 5476, 54107, 54S112, 54S113 P IN -O U T D IA G R A M S DESCRIPTION Th e se m o n o lith ic dual J -K flip -flo p s fe a tu re in d iv id u a l J, K ,

Contextual Info: SN54LS114A, 54S114, SN74LS114A, SN74S114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK M A R C H 1973 — R E V ISE D M A R C H 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance SN 54LS114A . SN 54S114

64LS11

Abstract: 74LS11M
Contextual Info: SN54LS11, 54S11, SN74LS11, SN74S11 TRIPLE 3 INPUT POSITIVE AND GATES APRIL 1 9 8 5 - R E V I S E D M A R C H 1 9B 8 • • Package Options Include Plastic "Sm all O utline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs

dy 255

Abstract: 74s405 H R C M F 2J 225 Fairchild 9960 nixie driver 9614 line driver ci 8602 gn block diagram FJH211 Fairchild msi cul9960 variable frequency circuit diagram using IC 555
Contextual Info: IN THE, BOSTON - 6 17- 4 4 * A SUBSIDiA) ./ OF DUCOMMUN INCORPOfiATED S, MASS vw . JU N E 1 97 S Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the

200N1

Abstract: 1N3064
Contextual Info: MIL-M-38510/80D 8 D E C E M B E R 1987 s u Pe r s ë d i n S MIL-M-38510/80C 21 N o v e m b e r 19 8 5 Q u a l i f i c a t i o n r e q u i r e m e n t s ar e ! r e m o v e d f o r d e v i c e t y p e s 02, I 04. Se e Sc o p e . _ 1 MICROCIRCUITS,

74s112n

Abstract: 54S112 74S112
Contextual Info: I R C H I L D S E M I C O N D U C T O R TM DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description sition tim e of th e negative going edge o f the clock pulse. Data on the J and K inputs can be changed w hile the clock

Contextual Info: TYPES SN54H11, SN54LS11, 54S11, SN74H11, SN74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE-AND GATES R E V IS E D A P R IL 1 S 8 5 Dependable Texas Instruments Quality and Reliability SN54H11 . . . J PACKAGE SN 54LS11, SN 54 S1 1 . . . J OR W PACKAGE SN 74H11 . . . J OR N PACKAGE

74s188 programming

Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
Contextual Info: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE

itt 7441

Abstract: transistor fcs 9012 7446 BCD to 7-segment Fairchild dtl catalog Truth Table 74192 7400 quad 2-input NAND gate truth-table 7449 BCD to 7-segment 7483 truth table Motorola Diode 54H01 semiconductors cross reference
Contextual Info: TTL DATA BOOK Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the Numerical Index. If you are trying to choose the best device for your application, consult the

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

SN7449

Abstract: 54175 SN7401 74L42 SN7437 SN74S40
Contextual Info: Ordering Instructions and Mechanical Data INTEGRATED CIRCUITS MECHANICAL DATA ORDERING INSTRUCTIONS Electrical characteristics presented in this catalog, unless otherwise noted, apply for circuit type s listed in the page heading regardless of package. Except for diode arrays, ECL, and MOS devices, the availability of a circuit function in a

Contextual Info: INCH-POUND MIL-M-38510/80E 10 August 2005 SUPERSEDING MIL-M-38510/80D 8 December 1987 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, SCHOTTKY TTL, AND GATES, MONOLITHIC SILICON Inactive for new design after 23 August 1996. This specification is approved for use by all Departments

bipolar PROM

Abstract: plhs18p8 S4LS04 82HS641 PLHS18 54175 82s137a 82S191 68172 54F04
Contextual Info: Signetics I Alphanumeric I Index Military Products H LM119 LM124 LM139 Vol. 1 17 Dual Voltage Comparator Vol.2 22 26 26 Low Power Quad Op Amp LM139A Qual Voltage Comparator Qual Voltage Comparator PLC18V8Z Zero Standby Power Universal PAL -Type Device PLC415

74s113a

Abstract: SN74LS113 74ls113a
Contextual Info: SN54LS113A, 54S113, SN74LS113A, SN74S113A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET D2661, APRIL 1982 - REVISEO MARCH 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 1 1 3 A , S N 5 4 S 1 1 3 . . . J OR W P A C K A G E

54s112

Abstract: 74LS112A 74S112
Contextual Info: SN54LS112A, 54S112, SN74LS112A. SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR _ Fully Buffered to Offer Maximum Isolation from External Disturbance • D 2 6 6 1 . A P R IL 1 9 8 2 - R E V I S E D M A R C H 1 9 8 8

DM54

Abstract: DM74 DM74S114
Contextual Info: ÆjA Semiconductor 54S114/DM74S114 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Common Clear, Common Clock and Complementary Outputs General Description Absolute Maximum Ratings Note d T h is d e v ic e c o n ta in s tw o n e g a tiv e -e d g e -trig g e re d J-K

54H11

Abstract: LS11 SN54LS11 SN54S11 SN74H11 SN74LS11 SN74S11
Contextual Info: TYPES SN54H11, SN54LS11, 54S11, SN74H11, SN74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE-AND GATES REV ISED APRIL 19SS Package Options Include Both Plastic and Ceram ic Chip Carriers in A ddition to Plastic and Ceram ic DIPs SN 54H 11 P A C K A G E S N 5 4 L S 1 1. S N 5 4 S 1 1 . . . J O R W P AC KA G E