54LS10 Search Results

Contextual Info: Z9A National SLA Semiconductor 54LS109/54LS109A/DM74LSJI09A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and

AS11JAN

Contextual Info: M M O T O R O L A M ilitary 54LS10 Triple 3-Input Positive IUAND Gate ELECTRICALLY TESTED PER: MIL-M-38510/30005 AVAILABLE AS: 11 JAN: JM38510/30005BXA 2) SMD: * 3) 883C . 54LS10/BXAJC LOGIC DIAGRAM Vcc Cl Y1 M ra f i C3 B3 it I > f Al A3 Y3 X = CASE OUTLINE AS FOLLOWS:

Contextual Info: LS109A National Semiconductor 54LS109/54LS109A/DM74LSJ09A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

54ls10

Contextual Info: Signetics I 54LS10, 54S10, 54S11 Gates Triple Three-Input NAND ’10 , AND (’11) Gates Military Logic Products H FUNCTION TABLE ORDERING INFORMATION INPUTS Product Specification DESCRIPTION OUTPUTS A B C Y(’10) Y('11) L L L L H H H H L L H H L L H H L

Contextual Info: June 1989 54LS109/54LS109A/DM74LSJ109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

DM74LS10N

Abstract: 54LS10 54LS10LMQB DM54LS10J DM54LS10W DM74LS10M E20A
Contextual Info: , June 1989 54LS10/54LS10/DM74LS10 Triple 3-Input NAND Gates General Description Features This device contains three independent gates each of which performs the logic NAND function. • Alternate Military/Aerospace device 54LS10 is available. Contact a National Semiconductor Sales Office/

Contextual Info: June 1989 Semiconductor 54LS10/54LS10/DM74LS10 Triple 3-Input NAND Gates General Description Features This device contains three independent gates each of which performs the logic NAND function. • Alternate Military/Aerospace device 54LS10 is available. Contact a National Semiconductor Sales Office/

Contextual Info: Signetics 54LS109 Flip-Flop Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION Th e 5 4 L S 1 09 is a dual positive edge-trig­ gered JR-type flip-flop featuring individual J, K, Clock, S et and R eset inputs; also

74LS10

Abstract: DM74LS10 DM74LS10N 54LS10 54LS10DMQB 54LS10FMQB 54LS10LMQB DM54LS10J DM54LS10W DM74LS10M
Contextual Info: DM74LS10 Triple 3-Input NAND Gates General Description This device contains three independent gates each of which performs the logic NAND function. Features n Alternate Military/Aerospace device 54LS10 is available. Contact a Fairchild Semiconductor Sales

Contextual Info: LS10 £ 2 National Semiconductor 54LS10/54LS10/DM74LS10 Triple 3-lnput NAND Gates General Description Features This device contains three independent gates each of which performs the logic NAND function. • Alternate Military/Aerospace device 54LS10 is avaiiable. Contact a National Semiconductor Sales Office/

Contextual Info: 54LS10,54LS10,DM74LS10 54LS10 54LS10 DM74LS10 Triple 3-Input NAND Gates Literature Number: SNOS277A 54LS10 54LS10 DM74LS10 Triple 3-Input NAND Gates General Description Features This device contains three independent gates each of which performs the logic NAND function

Contextual Info: M MOTOROLA Military 54LS109A Dual J-K Flip-Flop With Clear and Preset ELECTRICALLY TESTED PER: MIL-M-38510/30109 M The 54LS109A consists of two high-speed completely independent transition clocked J-K flip-flops. The clocking operation is independent of

Contextual Info: M M ilita ry 54L S 10 M O T O R O L A Triple 3-In pu t P ositive NAND G ate MP0 HUM ELECTRICALLY TESTED PER: MIL-M-38510/30005 LOGIC DIAGRAM Vcc C1 Y1 C3 B3 A3 Y3 AVAILABLE AS: 1) JAN: JM38510/30005BXA 2) SMD: N/A 3)883: 54LS10/BXAJC X = CASE OUTLINE AS FOLLOWS:

54LS109

Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AM DM74LS109AN J16A M16A
Contextual Info: June 1989 54LS109/54LS109A/DM74LSjK 9A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig£ered J-K flip-flops with complementary outputs. The J and

Contextual Info: June 1989 54LS10/54LS10/DM74LS10 Triple 3-Input NAND Gates General Description Features This device contains three independent gates each of which performs the logic NAND function. • Alternate Military/Aerospace device 54LS10 is available. Contact a National Semiconductor Sales Office/

Contextual Info: S E M IC O N D U C T O R tm DM74LS10 Triple 3-Input NAND Gates General Description This device contains three independent gates each of which perform s the logic NAND function. Features • Alternate M ilitary/Aerospace device 54LS10 is available. C ontact a Fairchild Sem iconductor Sales

Contextual Info: 54LS109,54LS109A,DM74LS109A 54LS109 54LS109A DM74LS109A Dual Positive-Edge-Triggered J- Flip-Flops with Preset, Clear, and Complementary Outputs Literature Number: SNOS278A 54LS109 54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs

Contextual Info: 54LS109 Signetics Flip-Flop Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION The 54LS109 is a dual positive edge-trig­ gered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also

54LS109

Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AN J16A M16A LS109 DM74LS109
Contextual Info: LS109A National Semiconductor 54LS109/54LS109A/DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and

54LS10

Abstract: DM74LS10 54LS10DMQB 54LS10FMQB 54LS10LMQB DM54LS10 DM54LS10J DM54LS10W DM74LS10M DM74LS10N
Contextual Info: 54LS10 54LS10 DM74LS10 Triple 3-Input NAND Gates General Description Features This device contains three independent gates each of which performs the logic NAND function Y Alternate Military Aerospace device 54LS10 is available Contact a National Semiconductor Sales Office

Contextual Info: M MOTOROLA Military 54LS107A Dual J -K Flip-Flop W ith C lear ELECTRICALLY TESTED PER: MIL-M-38510/30108 M The 54LS107A is a Dual J-K flip-flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH to LOW transition of the clock. A LOW signal on CD input overrides the

Contextual Info: M Military 54LS10 M O T O R O L A Triple 3-Input Positive NAND Gate MP0 mini ELECTRICALLY TESTED PER: MIL-M-38510/30005 LOGIC DIAGRAM V cc C1 Y1 C3 B3 A3 V3 AVAILABLE AS: 1) JAN: JM3B510/30005BXA 2) SMD: N/A 3)883: 54LS10/BXAJC X = CASE OUTLINE AS FOLLOWS:

54LS109

Abstract: 54LS109DMQB 54LS109FMQB DM54LS109A DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AM DM74LS109AN J16A
Contextual Info: 54LS109 54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs The J and K data is accepted by the flip-flop on the rising edge of the

Contextual Info: S E M IC O N D U C T O R tm DM74LS10 Triple 3-Input NAND Gates General Description This device contains three independent gates each of which performs the logic NAND function. Features • Alternate Military/Aerospace device 54LS10 is available. Contact a Fairchild Semiconductor Sales