74LS10 Search Results

ttl 74ls10

Abstract: truth table NOT gate 74 74LS10 74LS10 truth table 751A-02 SN54-74LS10 74LS10 TTL 3 input nand gate 74LS10
Contextual Info: SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

DN74LS10

Abstract: MA161
Contextual Info: I LS TTL DN74LS Series 74LS10 74LS10 T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption P,j = 6mW typical High speed ( tpd = 10ns typical)

DN74LS10

Abstract: MA161
Contextual Info: LS TTL DN74LS Series 74LS10 74LS10 bio74-LSto T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption Pd = 6mW typical High speed ( tpd = 10ns typical)

CI 7474

Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi (3 J Q 2 — J SD 0 CP Z o (3 11 4 K Ä 0 Co “LT in > _6 12 CP 3 -0 14 K Co ° 7 o-i- CP 13 —c K Cd °

74LS109PC

Contextual Info: 109 C O N N E C T IO N D IA G R A M PINOUT A /54S /74S 109 v o4LS/74LS109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — The '109 consists of tw o high speed, com pletely indepen­ dent transition clocked J K flip-flops. The clocking operation is independent

Contextual Info: GD54/74LS109A DUAL POSITIVE-EDGE- TRIGGERED J-K FLIP-FLOPS Feature Pin Configuration • Positive Edge-Triggering • Direct Set and reset inputs • J and K inputs • Q and Q outputs Vcc CLR2 J2 K2 C LK 2 PR2 Q2 QS R RRRFI R HR y Description This device contains two independent positiveedge-triggered J-K flip-flops with complementary out­

74LS107n

Abstract: 74107PC IC 74LS107
Contextual Info: 107 CONNECTION DIAGRAM P IN O U T A oft 54/74107 O ' 54LS/74LS107^ n o r D UAL JK FLIP-FLO P With Separate Clears and Clocks Ji ^ DESCRIPTION— T he '107 dual J K master/slave flip-flops have a separate clo ck for each flip-flop. Inputs to the master section are controlled by the

751A-02

Abstract: TTL 74LS10 3 input nand gate 74LS10 SN54-74LS10
Contextual Info: SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

74LS107A

Abstract: 74LS73A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS73
Contextual Info: SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the

74ls109

Contextual Info: MOTOROLA SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP T h e S N 5 4 /7 4 L S 1 0 9 A c o n sists of tw o high sp e e d c o m p le te ly in d e p e n d e n t tra n s itio n clo cke d JK flip -flo p s. T h e c lo c k in g o p e ra tio n is in d e p e n d e n t o f rise

Contextual Info: 107 AVG Semiconductors_ DDiT Technical Data 74LS107A DV74ALS107 Dual JK Negative Edge-Triggered Flip-Flop N Suffix Plastic DIP AVG-001Case The 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initialized by the HIGH-toLOW transition of the clock. A LOW signal on Clear input overrides the

TTL 74ls74

Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 ui 9 D UJ -=pi (3 J Q 2 — J SD 0 CP Z o (3 4 K Ä Co “LT in > </> O a 3 -0 K Co ° I- 3 a. I- 3 O 4-0 Co ? 15 D61 54/7474, 54H/74H74,

IC 74107

Abstract: IC 74LS107 74LS107 LS107
Contextual Info: Signelics 74107, LS107 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION transferred to the slave on the H IG H -toLO W Clock transition. For these devices TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74107 20MHz 20mA 74LS107 45MHz

74LSOO

Abstract: HD74LS109A
Contextual Info: H D 74LS109A . Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear IP IN ARRANGEMENT •REC O M M EN D ED OPERATING CONDITIONS S ym bol Item fr o c k C lock fre q u e n c y C lo c k High P u ls e w idth S r'.v lo w “ H " D a ta S e tu p tim e

jk flipflop

Abstract: DN74LS107 MA161
Contextual Info: I LS TTL DN74LS Series 74LS107 D N 74LS107 Dual J-K Flip-Flops with Reset P-1 • Description 74LS107 contains two negative-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K, and direct-coupled reset input terminals. ■ Features

TTL 7411

Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA

TTL 74ls74

Abstract: 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL M A S T E R /S LA V E E D G E -T R IG G E R E D D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi J Q (3 CP o K Z 2 — J SD 0 _6 Co (3 “LT in > z o Q J CP I- 3 a. 3 O So J - Ö K 4-0

RS flip flop IC

Abstract: M74LS109AP T flip flop pin configuration Toggle flip flop IC JK flip flop IC 20-PIN toggle type flip flop ic
Contextual Info: MITSUBISHI LSTTLs M 74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLO P WITH S E T AND R ESE T DESCRIPTION PIN C O NFIG URATIO N TOP V IEW The 74LS109AP is a semiconductor integrated circuit containing 2 J-K positive edge-triggered flip-flop circuits

M74LS107AP

Abstract: 74LS107AP M74LS73AP 20-PIN 74ls107a 74LS107* pin and application
Contextual Info: M IT S U B IS H I LSTTLs 74LS107AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS W ITH RESET DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS107A P conta in in g 2 J -K is a sem ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits

74LS109A

Abstract: SN54/74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 751B-03
Contextual Info: SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D

CI 7410

Abstract: CI 74ls10 74LS10 74LS10 pin configuration N7410F N7410N N74H10F N74H10N N74LS10F N74LS10N
Contextual Info: PIN CONFIGURATIONS 54/7410 54H/74H10 54S/74S10 54LS/74LS10 ORDERING CODE See Section 9 for further Package and Ordering Information. Œ *14*] VCC Œ E m m m [I 2Sl Œ 3 Œ PACKAGES C O M M E R C IA L RANGES to »70"C PIN CONF. VCC - 5V * 5"/o; T a = 0°C

TTL 7410

Abstract: ua 7411 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 TTL 7411 74LS10 pin configuration 7411 pin configuration 74LS11 function table 74ls 7410 pin configuration
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products • Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns

74LS109AP

Abstract: M74LS109 flip flop RS M74LS109AP
Contextual Info: MITSUBISHI LSTTLs M 74LS109A P DUAL J-K P O S IT IV E EDGE-TRIGGERED F L IP FLOP W IT H SET AND RESET DESCRIPTION PIN CONFIGURATION TOP VIEW The 74LS109AP is a semiconductor integrated circu it containing 2 J-K positive edge-triggered flip -flo p circuits

74LS10 truth table

Contextual Info: g M O TO R O LA SN54/74LS10 R R R R R FI R -= 5 > TRIPLE 3-INPUT N A N D GATE LOW POWER SCHOTTKY LLl LlI ÜJ LlI LlI Li J LI J Suffix — Case 632-08 (Ceramic) N Suffix — Case 646-06 (Plastic) GUARANTEED OPERATING RANGES MIN TYP MAX UNIT V CC SYM B O L