500NS Search Results

Contextual Info: □BQ ILC DATA DEVICE CORPORATION_ _ _ ADC-00300" and ADC-00302 12 BIT 2 MHz T/H + A/D HYBRID HIGH SPEED, SMALL SIZE FEATURES ADC-00300 DESCRIPTION The ADC-00300 is a 12 bit, 500nsec 2 MHz track/hold and A/D converter hy­ brid in 40 pin TDIP or flatpack packages.

BY218

Abstract: BUV56A TEA2164 TEA5170 input 12v output 6-9 volt BY-218 bc547c w 68 philips capacitor 250V 220uf SGS-Thomson BA159 philips capacitor 1000uf 25V
Contextual Info: TEA5170 SWITCH MODE POWER SUPPLY SECONDARY CIRCUIT . . . . . . INTERNAL PWM SIGNAL GENERATOR POWER SUPPLY WIDE RANGE 4.5V – 14.5V SOFT START REFERENCE VOLTAGE 2V ± 5% WIDE FREQUENCY RANGE 250kHz MINIMUM OUTPUT PULSE WIDTH 500nS MAXIMUM PRESET DUTY CYCLE

voltage level shifter 3.3V to 5V

Contextual Info: DAC1264X_RA3 0.18µ µ m 3.3V 10-BIT 2MSPS 8-CHANNEL DAC GENERAL DESCRIPTION The dac1264x_ra3 is a CMOS 10Bit 8-channel D/A converter for general application. This digital to analog converter has a 10bit R-string structure. Its settling time is 500ns Typical value .

2n2700

Contextual Info: LT6119-1/LT6119-2 Current Sense Amplifier, Reference and Comparators with POR Description Features Current Sense Amplifier – Fast Step Response: 500ns – Low Offset Voltage: 200µV Maximum – Low Gain Error: 0.2% Maximum n Internal 400mV Precision Reference

Contextual Info: ykiyjxivki 19-1193; Rev0; 4/97 16-Channel/Dual 8-Channel, Lo w -Lea kage , CMOS A n a lo g M u lt ip le x e r s _ F e a t u r e s ♦ <400£2 max On-Resistance ♦ <500ns Transition Time ♦ <10£2 On-Resistance Match ♦ <20pA NO-Off Leakage Current at +25 °C

Contextual Info: SILICON NPN EPITAXIAL TYPE 2SC4409 POWER A MPLIFIER APPLICATIONS. Unit in m m POWER SWITCHING APPLICATIONS. 1.6MAX0.4 ±0.05,. 1.7 MAX- . Low Collector Saturation Voltage : VC E sat =0.5V(Max.)(at Ic=lA) . High Speed Switching Time : tstg=500ns(Typ.) . Small Flat Package

2SA1681

Abstract: 2SC4409
Contextual Info: 2SC4409 TOSHIBA Transistor Silicon NPN Epitaxial Type PCT Process 2SC4409 Power Amplifier Applications Power switching applications Unit: mm • Low collector saturation voltage: VCE (sat) = 0.5V (max) (at IC = 1A) • High speed switching time: tstg = 500ns (typ.)

79PR1K

Abstract: Model 48J 50k trimpot AC1010 settling time
Contextual Info: Fast Settling Differential FET Op Amp ANALOG DEVICES □ FEATURES Fast Settling: 500ns max Fast Slew Rate: 125V/,us Wide Bandwidth: 15MHz High Com m on Mode Rejection: 83«1B min High Gain: A 0 = 100,000 Low Drift: 15m V/°C 48K A P P L IC A T IO N S Stable Unity Gain Buffer to 15MHz

Contextual Info: lawprofile t 2l COMPATIBLE ffi>CIC DELAY DULES FOR ^^AUTOMATIC EOUIPMENT INSERTION # # # # # # # T 2 l input and outputs Delays stable and precise 14-pin DIP package .240 high Supplied in tubes for automatic insertion Available in delays from 25 to 500ns

g12n60d1

Abstract: AN7254 AN7260 HGTP12N60D1 G12N60D
Contextual Info: HGTP12N60D1 12A, 600V N-Channel IGBT April 1995 Features Package • 12A, 600V JEDEC TO-220AB • Latch Free Operation EMITTER COLLECTOR • Typical Fall Time <500ns GATE • High Input Impedance COLLECTOR FLANGE • Low Conduction Loss Description The IGBT is a MOS gated high voltage switching device

BUV56A

Abstract: TEA2164 synchro amplifier schematic bc547c w 68 smps isolated 12v output 90w TEA5170 AN408 china tv schematic diagram free by218 12v 1a smps circuit diagram
Contextual Info: TEA5170 SWITCH MODE POWER SUPPLY SECONDARY CIRCUIT . . . . . . INTERNAL PWM SIGNAL GENERATOR POWER SUPPLY WIDE RANGE 4.5V – 14.5V SOFT START REFERENCE VOLTAGE 2V ± 5% WIDE FREQUENCY RANGE 250kHz MINIMUM OUTPUT PULSE WIDTH 500nS MAXIMUM PRESET DUTY CYCLE

Contextual Info: SGS-THOMSON HD E[fil IILICÎ^(â IKlDSl ST9040 16K ROM HCMOS MCU WITH EEPROM, RAM AND A/D CONVERTER • Register oriented 8/16 bit CORE with RUN, WFI and HALT modes ■ Minimum instruction cycle time : 500ns (12MHz internal) ■ Internal Memory : ROM 16K bytes

Contextual Info: UC1714/5 UC2714/5 UC3714/5 application INFO available Complementary Switch FET Drivers FEATURES DESCRIPTION • Single Input PWM and TTL Compatible • Time Delays Between Power and Auxiliary Outputs Independently Programmable from 50ns to 500ns These two families of high speed drivers are designed to provide drive

EMM Semi

Abstract: rom 1024 1024x8 8108-3CD 8108-5CD SEMI8108 1024x8 ram EMM 8108 ram 8108
Contextual Info: SEMI 8108 300NSEC, STATIC, T T L IN/OUT 1024 X 8 N-MOS RAM SEMI 8108 500NSEC, STATIC, T T L IN/OUT 1024 X 8 N-MOS RAM FE A T U R E S G E N E R A L D E S C R IP TIO N E M M S E M I'S 8 1 0 8 is a 8 1 9 2 - b it s ta tic R A M , • 1 0 2 4 w o rd s X 8 b its

D0200

Contextual Info: LOW VOLTAGE RECTIFIERS 150-500nS RECOVERY y AXIAL LEADED HERMETICALLY SEALED MIL-S-19500/429 1N5615 thru 1N5623 1N5615 1N5617 = 200-1000V = 1 5A cnn e = 150-500nS , _F T rr A B C D .185 Max 4.7 .110(2.8) Max .065(1.65) Min ,033(,838) Max ,026(.66) Min 1.30(33.02)

Contextual Info: PCI 9050 Single Cycle Write What is the relationship between NRAD, NRDD, NXDA, NWAD, NWDD, etc.? 0ns 250ns 500ns LCLK ADS# BLAST# LA[27:2] ADDR LAD[31:0] ADDR DATA DATA WAITO# WR# LW/R# LRDYi# Write Strobe Delay Example=1 NWAD Example=2 Data Transfered Write Cycle Hold

Contextual Info: lew?profile ECL COMPATIBLE LOGIC NOISE FILTER MODULE # # # # # ECL input and output Pulse Width Detection stable and precise 16-pin DIP package .250 high Available in pulse widths from 5ns to 500ns 70 ECL DC fan-out capacity design notes The ECLNFM is offered in 24 pulse w idths fro m 5ns to 500ns,

Contextual Info: T L C O M PA TIBLE H-OCIC MODULE # T2 L in p u t and o utp uts # Delays stable and precise % 8-pin Space Saver package Leads - thru-hole, J, Gull W ing o r Tucked # A vailable in delays from 10 to 500ns # O utput and fo u r 4 taps - each isolated and w ith 10 T2L fan-out capacity

D567

Abstract: AD567JD
Contextual Info: AN ALO G D E V IC E S Microprocessor-Compatible 12-Bit D/A Converter AD567 FEA TU R E S Single Chip Construction Double-Buffered Latch for 8-B it juP-Compatibility Fast Settling Time: 500ns max to ±1/2LSB High Stability Buried Zener Reference on Chip Monotonicity Guaranteed Over Temperature

Contextual Info: iozv profite t 2l COMPATIBLE DIP LOGIC DELAY LINE M iNÏ j # T2 L FAST in p ut and o u tp u t # Delay stable and precise # 8-pin DIP package # L e a d s -T h ru -h o le , J, Gull W ing or Tucked # A vailable in delays fro m 5 to 500ns # O utput isolated and w ith 10 T2L fan-out

Contextual Info: ACTIVE DIGITAL DELAY LINES R ESSTO RS *CM>S&COILS -DELAY LINES A01 SERIES (SINGLE DELAY) A03 SERIES (TRIPLE DELAY) FEATURES □ □ □ □ □ Economical cost, prompt delivery! Wide range of values, 10nS to 500nS. TTL compatible Operating temperature: 0°C to 70°C

Contextual Info: la*profile t 2l COMFATIBLE DIP LOGIC DELAY MODULE M ini # T2|_ input and outputs # # Delays stable and precise 8-pin DIP package .250 high # 9 Available in delays from 25 to 500ns 20% taps — each isolated and with 10 Schottky t 2|_ fan-out capacity Fast rise time on all outputs

ADSHC-85

Abstract: ADC84 HAS0802 ADSHC-85ET
Contextual Info: □ AN ALO G D EV IC ES Fast 0.01% Track/Sample-and-Hold Amplifiers FEATURES Improved SHC-85 Replacement 500ns Sample-to-Hold Transient 50|iV rms Noise Low Droop Rate of 0.2mV/ms ADSHC-85 ADSHC-85 FUNCTIONAL BLOCK DIAGRAM w ¿k I U I 5k T ^ A A r- -l A PPLICA TIO N S

56-G2015-000B

Contextual Info: XX-XXXX; Rev 1; 11/03 3V 10-Tap Silicon Delay Line The DS1110L 10-tap delay line is a 3V version of the DS1110. It has 10 equally spaced taps providing delays from 10ns to 500ns. The DS1110L series delay lines provide a nominal accuracy of ±5% or ±2ns, whichever