LS107 Search Results

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C74HC107 Dual J -K Flip-Flop w ith Reset High-Performance Silicon-Gate CMOS The MC74HC107 is identical in pinout to the LS107. The device inputs are com patible with standard CMOS outputs; with pullup resistors, they are

Contextual Info: LS73 LS76 LS107 LS112 Dual J-K Negative-Edge-Triggered Flip-Flops LS113 •Pin-for-Pin and functional equivalents to 5473, 5476, 54107, 54S112, 54S113 PIN-OUT DIAGRAMS DESCRIPTION These monolithic dual J-K flip-flops feature individual J, K, clock, and asynchronous preset and clear inputs to each

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C74HC107 Dual J -K Flip-Flop w ith Reset High-Performance Silicon-Gate CMOS The MC74HC107 is identical in pinout to the LS107. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are

74HC107

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC107 Dual J-K Flip-Flop w ith Reset High-Performance Silicon-Gate C M O S The M C 54/74H C 10 7 is id en tica l in p in o u t to the LS107. The device in p u ts are co m p a tib le w ith standard C M O S o u tp u ts ; w ith p u llu p resistors, they are c o m p a tib le

4027B

Abstract: 4013B hc374 HC-377 HC76 flip-flop HC-107 4027B equivalent hc175 HCT74
Contextual Info: SELECTION GUIDE FLIP-FLOP Type Number M54/74 Functional Equivalent LSTTL 54/74 Function Suggested Alternative LS 54/74 4000B Functional Equivalent CMOS 4000B Package DIP LS73 LS74 LS74 LS76 LS107 4027B 4013B 4013B 4027B 4027B 14 14 14 16 14 Dual J-K FLIP-FLOP with Preset and Clear

LS107

Abstract: HC107 DL129 HC73 MC74HC107 MC74HCXXXD MC74HCXXXN
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC74HC107 Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC107 is identical in pinout to the LS107. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are

74107 pin diagram

Abstract: CI 74107 74ls107 pin configuration 74LS107 TTL 74107 2RD22 74107 LS107 1N3064 1N916
Contextual Info: Signetics 74107, LS107 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The ’107 is a dual flip-flop with individual J, K, Clock and direct Reset inputs. The 74107 is a positive pulse-triggered flip­ flop. JK information is loaded into the

IC 74107

Abstract: IC 74LS107 74LS107 LS107
Contextual Info: Signelics 74107, LS107 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION transferred to the slave on the H IG H -toLO W Clock transition. For these devices TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74107 20MHz 20mA LS107 45MHz

pin configuration 74LS107

Abstract: 74LS107 LS107 LS-107 74107 AN ttl 74107 74107 pin configuration N74107
Contextual Info: 74107, LS107 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '107 is a dual flip-flop with individual J, K, Clock and direct Reset inputs. The 74107 is a positive pulse-triggered flipflop. JK information is loaded into the

MC54HC107

Contextual Info: MOTOROLA SEM IC O N D U C TO R TECHNICAL DATA MC54/74HC107 Dual J-K Flip-Flop w ith Reset H ig h -P erfo rm an ce S ilicon-G ate C M O S J SUFFIX CERAMIC CASE 632-08 The M C 54/74H C 10 7 is iden tical m p in o u t to th e LS107. The device in p u ts are c o m p a tib le w ith standard C M O S o u to u ts ; w ith pull up resistors, they are c o m p a tib le

LS107

Abstract: LS112 LS76 LS113 54S112 54S113 LS73 raytheon 74
Contextual Info: LS73 LS76 LS107 LS112 Dual J-K Negative-Edge-Triggered Flip-Flops _ LS113 •Pin-for-Pin and functional equivalents to 5473, 5476, 54107, 54S112, 54S113 P IN -O U T D IA G R A M S DESCRIPTION Th e se m o n o lith ic dual J -K flip -flo p s fe a tu re in d iv id u a l J, K ,

6367-1

Contextual Info: LS107A National Semiconductor LS107A/LS107A Dual Negative-EdgeTriggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

74107 pin diagram

Abstract: 74107 74LS107 74107 flip flop H/CI 74107 pin configuration 74LS107 1N3064 1N916 74LS LS107
Contextual Info: 74107, LS107 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION Th e '1 0 7 is a dual flip-flop with individual J, K, Clock and direct R eset inputs. The 7 4 1 0 7 Is a positive pulse-triggered flip­ flop. JK information is loaded into the

IC 74107

Abstract: H/IC 74107 LS-107 LS107 pin configuration 74LS107
Contextual Info: Signetics 74107, LS107 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION m a s te r w h ile th e C lo c k is H IG H and tra n s fe rre d to th e s la v e o n th e H IG H -to - TYPICAL fMAX TYPICAL SUPPLY CURRENT TOTAL 74107 20MHz

74107PC

Abstract: 74ls107 74LS107DC 74107 pin diagram 54LS107DM LS107 54107DM 54107FM 74107DC 74107FC
Contextual Info: 107 C O N N E C T IO N D IA G R A M P IN O U T A 54/74107 '54LS /74LS 107 e> DUAL JK FLIP-FLOP With Separate Clears and Clocks D E S C R IP T IO N — T h e '107 d u a l J K m aster/slave flip -flo p s have a separate c lo c k fo r each flip -flo p . In p u ts to th e m aster se ctio n are c o n tro lle d b y the

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

Contextual Info: SG60R4 Schottky TTL • Over 180 LS Devices • ALS • FAST TOTAL TTL COMMITMENT «TOTAL • TTL Compatible Macrocell Arrays • RAMs • PROMs General Information TTL in Perspective proved speed — p o w e r product co m p ared to LS as a result o f ad vanced M O S A IC oxide isolated processing.

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

mc68701 probug

Abstract: MC144100 M68KVM02 user manual m6809 EXORCISER motorola MC146805G2 MC1468705G2 AN/mc68701 probug
Contextual Info: Motorola’s Microcomputer Families i Reliability Data Sheets Mechanical Data E Technical Training Memory Products Logic and Special Function Products Development Systems and Board-Level Products E M motorola MICROCOMPUTERS Prepared by Technical Information Center

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

ls307

Abstract: Ic C 141a LS107
Contextual Info: s g s-thom son d ? e d 752=1537 ODllbSt. 5 H & - / ¿> TS107 LS207 LS 307; 7929225 S G S S E M IC O N D U C T O R C O R P ELECTRICAL CHARACTERISTICS {see note L S 307 L S 107/LS 207 Parameter Unit T est co n d itio n s In p u t offset voltage R g < 10 k i î

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
Contextual Info: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher