74192 Search Results

74192

Abstract: 74193 NAFI 74LSI92 BCD counter 74LS193 74193 A 74192 counter
Contextual Info: — 152 — 74192 Presettable Synchronous Up/Down BC D Counter dual clock, with clear ' NPVTS *cc * OUTP UTS I NP UT S ^ ^ •tmwow c p 1 A A C L C A H K M IR O W C A f A A I Or On XX DAT* 0B Q. COUN I COUNT G ND o i \ i - v Y m W - £ T ' v - r r < j > U O > ? ( &9 i J A * )

ic 74192 pin diagram

Abstract: LA 4289 74192 ic 74192 counter ic 74192 74ls192 74192PC
Contextual Info: 192 C O N N E C T IO N DIAGRAM PINOUT A 54/74192 6 / * ° ^ 54LS/74LS192 O l o ü U ^ UP/DOWN DECADE COUNTER With Separate Up/Down Clocks P i[ T Tèi vcc o ,H H J po Qod 33 MR [7 T5] t c d CPd CPuU D ESCRIPTIO N — T h e ’ 192 is an u p /d o w n B C D d e c a d e (8421) co u n ter. S e p a ­

ci 74192

Abstract: 74192 TTL 74192 pin diagram of 74192 74192 counter
Contextual Info: TTL IN T E G R A T E D C IR C U IT S U P / D O W N D E C A D E C O U N T ER 74192 276-1831 GENERAL DESCRIPTION T h * ’ 74 Mil; |ji' ,sct is <i T T L . to a n v up-down number c h r o n o u s m i r y o' lm;n dc< ad-: (I t h r o u g h counter <i. winch load

TTL 74192

Abstract: 74193 counter ttl 74193 pin diagram of 74192 74192 counter 74193 state diagram 74193 state diagram up counter 74193 74192 74193 A
Contextual Info: TTL/MSI 9360/54192, 74192 9366/54193, 74193 UP/DOWN DECADE AND BINARY COUNTERS DESCRIPTIO N - The T T L /M S I 9360/5 4 1 9 2 , 74192 is a synchronous Up/Down BCD Decade Cbunter, and the T T L /M S I 9366/5 4 1 9 3 , 74193 is a synchronous Up/Down 4-Bit Binary Counter. Both counters have separate up/down clocks, parallel load facility, terminal

74192 internal diagram

Abstract: 74192FC 74LS192P 74LS192DC 74LS192 INTERNAL DIAGRAM 74192 counter
Contextual Info: 1 NATIONAL SEMICOND -CLOGIO DEE D | b S D U B S _ ~ T - 9 5 DDbBiei 5 | 3 -o 9 192 CO NN ECTIO N DIAGRAM PINO UT A 54/74192 54LS /74LS192 \ UP/DOWN DECADE COUNTER I P i[T 161Vcc o.QE H ] po Qo [T With Separate U p/D ow n Clocks

ic 74192 pin configuration

Abstract: pin diagram of counter ic 74193 ic 74193 ic 74192 ic 74192 pin diagram 74192 ic TTL 74192 ttl 74193 74192 pin configuration IC 74LS192
Contextual Info: Sìgnetìcs 74192, 74193, LS192, LS193 Logic Products FEATURES • Synchronous reversible 4-bit binary counting • Asynchronous parallel load • Asynchronous reset clear • Expandable without external logic 1 Counters TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT

74193 pin configuration

Abstract: ic 74192 74LS192 PIN CONFIGURATION ic 74193 ic 74192 pin configuration IC 74LS192 pin configuration of 74193 74 LS 193 Logic DIAGRAM ttl 74193 74193 state diagram
Contextual Info: Signetics 74192, 74193, LS192, LS193 Logic Products FEATURES • Synchronous reversible 4-bit binary counting • Asynchronous parallel load • Asynchronous reset clear • Expandable without external logic DESC RIPTIO N The ' 192 and ’ 193 are 4-bit synchronous

74192 pin configuration

Abstract: 74LS192 PIN CONFIGURATION TTL 74192 74192 74192 four bit binary counter 74193 state diagram up counter 74193 pin configuration 74192 up/down decade (0-9) counter 74193 pin diagram of 74192
Contextual Info: 74192, 74193, LS192, LS193 Signetics Counters '192 Presettable BCD Decade Up/Down Counter '193 Presettable 4-Bit Binary Up/Down Counter Product Specification Logic Products FEATURES TYPICAL f „ AX TYPICAL SUPPLY CURRENT 74192 32M H z 65m A 74LS 192 32M H z

ic 74192

Abstract: pin diagram of counter ic 74193 LM 74192 ic 74192 pin configuration ic 74193 74192 counter 74192 pin configuration 74193 pin configuration 74192 ic 74192
Contextual Info: 74192, 74193, LS192, LS193 Signetics Logic Products 1 Counters FEATURES TY PE • Synchronous reversible 4-bit binary counting • Asynchronous parallel load • Asynchronous reset clear • Expandable without external logic T Y P IC A L f „ AX T Y P IC A L SU PP LY C U R R E N T

Truth Table 74192

Abstract: pin diagram of counter ic 74193 74193 truth table ic 74192 74192 ic Truth Table 74193 of IC 74193 TC40192BPJC40193BP IC TTL 74193 TC40192BP/TC40193BP
Contextual Info: TC40192BPJC40193BP C2M 0 S DIGITAL INTEGRATED CIRCUIT SILICO N MONOLITHIC TC40192BP PRESETTABLE BCD UP/DOWN COUNTER Dual Clock with Reset TC40193BP PRESETTABLE BINARY UP/DOWN COUNTER (Dual Clock with Reset) T C 4 0 1 9 2 B P / T C40193BP i synchronous 4-bit up/down

dy 255

Abstract: 74s405 H R C M F 2J 225 Fairchild 9960 nixie driver 9614 line driver ci 8602 gn block diagram FJH211 Fairchild msi cul9960 variable frequency circuit diagram using IC 555
Contextual Info: IN THE, BOSTON - 6 17- 4 4 * A SUBSIDiA) ./ OF DUCOMMUN INCORPOfiATED S, MASS vw . JU N E 1 97 S Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the

32107

Abstract: SST27SF256 oasis TTL 7452 A115 32-PIN A103 A114 Tekelec TA 27721
Contextual Info: 256 Kilobit 32K x 8 SuperFlash MTP SST27SF256 Preliminary Specifications FEATURES: • 5.0V Read Operation (4.5V to 5.5V) • Superior Reliability – Endurance: At least 1000 Cycles – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 20 mA (typical)

TC40193BP

Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC40192BP,TC40193BP TC40192BP PRESETTABLE BCD UP/DOWN COUNTER Dual Clock with Reset TC40193BP PRESETTABLE BINARY UP/DOWN COUNTER (Dual Clock with Reset) TC40192BP/TC40193BP synchronous 4-bit up/down counter.

B083D

Abstract: u82720 A110D TDA4100 ub8830d V40511D taa981 A109D sy 710 IC 7447
Contextual Info: > i ! U O i j q > i a | a S [ ^ ] 0 [ y y H erstellerbetriebe Bei den einzelnen Erzeugnissen werden die Herstellerbetriebe durch die nachfolgend angegebenen Symbole gekennzeichnet: VEB M ik ro e le k tro n ik „K a rl M a r x “ Erfurt L e itb e tr ie b im VEB K o m b in a t M ik ro e le k tr o n ik

diode E1110

Abstract: lN4002 LN4003 ANA 618 20010 TDB 0123 km b3170 E1110 Diode UB8560D MAA723 moc 2030
Contextual Info: elektronik-bauelem ente I WT VD AVL 1 /8 7 Bl. 2 E r l ä u t e r u n g e n z u m I n h a l t und zu d e n A n g a b e n d e r B a u e l e m e n t e - V e r g l e i c h s l i s t e D ie B a u e l e m e n t e - V e r g l e i c h s l i s t e e n t h ä l t a l l e in d e r B i l a n z v e r a n t w o r t u n g d e s V E B K o m b i n a t

CI 7473

Abstract: counter with 7473 7490 Decade Counter 7476 up down counter 7476 counter ci 74192 decade counter 7492 74122 Retriggerable Monostable Multivibrator ci 7476 7490 counter
Contextual Info: BIPOLAR DIGITAL ICs continued :lip-flops T 7472/5472 T 7473/5473 T 7474/5474 T 7476/5476 T 74107/54107 T 74121/54121 T 74122/54122 T 74123/54123 Jther functions T 7441 A/5441 A T 7442/5442 T 7443/5443 T 7444/5444 T 7475/5475 T 7481/5481 T 7483/5483 T 7484/5484

7406n

Abstract: 7408n 74193N 7416N 7407N 74181N 74LS01N 7438N 7437N 74h00n
Contextual Info: CYFROWE UKtADY SCALONE TTL SERII UCY 74 . /UCA 64 . Wykaz oznaczen parametrów technicznych poj'emnosc Unii statyczny wspólczynnik wzmocnienia pr^dowego w ukladzie OE "21B pr^d bazy IB IC pr^d kolektora Icc pr^d zasilania ICC+ ICC" OD 011 ICCH ICCH-*'

7486 XOR gate

Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
Contextual Info: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier­

TTL 74139

Abstract: 74153 mux MSI 74148 16cudslr CI 74138 sn 74373 8mcomp 7404 7408 7432 7408, 7404, 7486, 7432 Flip-Flop 7471
Contextual Info: PLSLIB-TTL /$ ^ n^ X LIBRARY • TTL MacroFunction Library Diskette. • ADLIB, Altera Design Librarian Diskette. To increase design ease and productivity Altera has created M acroFunctions. These are high level building blocks that allow the user to design at

IC 74192

Abstract: working of ic 74123 MC4024 application circuits of ic 74123 sm0vpo 74192 ic MC4044 74192 frequency synthesizer HF receiver circuit 500Khz resonator
Contextual Info: SYNTHESISED HF RECEIVER by SM0VPO 1 of 2 http://w1.859.telia.com/~u85920178/rx/synth.htm SYNTHESISED HF RECEIVER by Harry Lythall - SM0VPO This receiver was originally designed for simplicity and low cost, but, like other projects, it grew. My receiver is now synthesized and the performance is quite

SO-16-narrow

Abstract: 6TPB330M D03IN1511 elektronik DDR STPS3L25U smd diode S4 6A 77121A7 transistor smd q46 L6910 L6910A
Contextual Info: L6910 L6910A ADJUSTABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 ■ ■ ■ ■ 3 Figure 1. Packages FEATURES OPERATING SUPPLY VOLTAGE FROM 5V TO 12V BUSES UP TO 1.3A GATE CURRENT CAPABILITY

TA 7644 BF

Abstract: cmos power TCP 8108 NEXUS FLASH ERASE oasis TCP 8108 32-PIN F01A SST31LH041 830049
Contextual Info: 4 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH041 Advance Information FEATURES: • Organized as 512K x 8 Flash + 128K x 8 SRAM • Latched Address and Data for Flash • Single 3.0-3.6V Read and Write Operations • Flash Fast Sector Erase and Byte Program:

Contextual Info: iiili 8 Megabit 1M x 8-Bit Multi-Purpose Flash _ SST39VF080Q_ Advance Information FEATURES: • Organized as 1M x 8 • Latched Address and Data • Single 2.7-3.6V Read and Write Operations • Fast Sector Erase and Byte Program:

Contextual Info: 21Ü 16 Megabit FlashBank Memory SST38UF166 Advance Information FEATURES: • • • Single 2.2-2.8V Read and Write Operations Read Access Time Separate Memory Banks for Code or Data - - Latched Address and Data Superior Reliability End of Write Detection