54LS109 Search Results

Contextual Info: Z9A National SLA Semiconductor 54LS109/54LS109A/DM74LSJI09A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and

Contextual Info: LS109A National Semiconductor 54LS109/54LS109A/DM74LSJ09A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

Contextual Info: June 1989 54LS109/54LS109A/DM74LSJ109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

Contextual Info: Signetics 54LS109 Flip-Flop Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION Th e 5 4 L S 1 09 is a dual positive edge-trig­ gered JR-type flip-flop featuring individual J, K, Clock, S et and R eset inputs; also

Contextual Info: M MOTOROLA Military 54LS109A Dual J-K Flip-Flop With Clear and Preset ELECTRICALLY TESTED PER: MIL-M-38510/30109 M The 54LS109A consists of two high-speed completely independent transition clocked J-K flip-flops. The clocking operation is independent of

54LS109

Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AM DM74LS109AN J16A M16A
Contextual Info: June 1989 54LS109/54LS109A/DM74LSjK 9A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig£ered J-K flip-flops with complementary outputs. The J and

Contextual Info: 54LS109,54LS109A,DM74LS109A 54LS109 54LS109A DM74LS109A Dual Positive-Edge-Triggered J- Flip-Flops with Preset, Clear, and Complementary Outputs Literature Number: SNOS278A 54LS109 54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs

Contextual Info: 54LS109 Signetics Flip-Flop Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION The 54LS109 is a dual positive edge-trig­ gered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also

54LS109

Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AN J16A M16A LS109 DM74LS109
Contextual Info: LS109A National Semiconductor 54LS109/54LS109A/DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and

54LS109

Abstract: 54LS109DMQB 54LS109FMQB DM54LS109A DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AM DM74LS109AN J16A
Contextual Info: 54LS109 54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs The J and K data is accepted by the flip-flop on the rising edge of the

54LS109A

Abstract: 54LS109A/BEAJC
Contextual Info: M MOTOROLA M ilitary 54LS109A Dual J -K Flip-Flop W ith C le ar and P reset ELECTRICALLY TESTED PER: MIL-M-38510/30109 M The 54LS109A consists of two high-speed completely independent transition clocked J-K flip-flops. The clocking operation is independent of

74LS109PC

Contextual Info: 109 C O N N E C T IO N D IA G R A M PINOUT A /54S /74S 109 v o4LS/74LS109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — The '109 consists of tw o high speed, com pletely indepen­ dent transition clocked J K flip-flops. The clocking operation is independent

Contextual Info: SN54109, 54LS109A, SN74109, SN74LS109A DUAL J-K POSITIVE-EDGE TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR DECEMBER 1983 - REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

SN74109

Abstract: LS109A SN54109 SN54LS109A SN74 SN74LS109A rv101
Contextual Info: SN54109, 54LS109A, SN74109, SN74LS109A d u a l j k p o sitiv e e d ge -trigge re d flip -flo p s w ith p re se t and c le a r s d l s 037 DECEMBER 1 9 8 3 - • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

LS74

Abstract: 54LS109 LS109 4 jn
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 04/24/98 Last Update Date: 09/14/98 Last Major Revision Date: 07/07/98 54LS109-X REV 1A0 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP General Description The 'LS109 consists of two high-speed, completely independent transition clocked

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

54LS641

Abstract: CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623
Contextual Info: MAXIMUM RATINGS Supply Voltage - Vcc T h e S e rie s 5 4 L S /7 4 L S Schottky TTL family features both Schottky-barrier-diode inputs and em itte r inputs and u tilizes full Schottky-barrier-diode clamping to achieve speeds com parable to Series 54/74 at one-fifth of the

bipolar PROM

Abstract: plhs18p8 S4LS04 82HS641 PLHS18 54175 82s137a 82S191 68172 54F04
Contextual Info: Signetics I Alphanumeric I Index Military Products H LM119 LM124 LM139 Vol. 1 17 Dual Voltage Comparator Vol.2 22 26 26 Low Power Quad Op Amp LM139A Qual Voltage Comparator Qual Voltage Comparator PLC18V8Z Zero Standby Power Universal PAL -Type Device PLC415

LG color tv Circuit Diagram schematics

Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
Contextual Info: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS

54LS109

Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AN J16A M16A
Contextual Info: E M IC D N D U C T O R t General Description This device contains tw o independent positive-edge-triggered J-K flip-flops w ith com plem entary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. T he triggering occurs at a vo lt­

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package