DM54 Search Results

Contextual Info: DM5438,DM7438 DM5438 DM7438 Quad 2-Input NAND Buffers with Open-Collector Outputs Literature Number: SNOS255A DM5438 DM7438 Quad 2-Input NAND Buffers with Open-Collector Outputs General Description Pull-Up Resistor Equations RMAX e VCC Min b VOH N1 (IOH) a N2 (IIH)

6506-1

Abstract: DM7420N 5420DMQB 5420FMQB DM5420 DM5420J DM5420W DM7420 J14A N14A
Contextual Info: 5420 DM5420 DM7420 Dual 4-Input NAND Gates General Description Features This device contains two independent gates each of which performs the logic NAND function Y Alternate Military Aerospace device 5420 is available Contact a National Semiconductor Sales Office Distributor for specifications

DM54L73W

Abstract: C1995 DM54L73 DM54L73J J14A W14B
Contextual Info: DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops after a complete clock

DM54LS174

Abstract: 54LS174 54LS174DMQB 54LS174FMQB 54LS175 DM54LS175 DM74LS174 DM74LS175 LS174 LS175
Contextual Info: 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad 175 versions feature complementary

74LS90N

Abstract: 74LS93N om504 74ls90 function 74LS93 logic symbol 54LS90 54LS92 DM54LS90 NSB50 CI 74LS90
Contextual Info: DM54LS90/DM74LS90, DM54LS92/DM74LS92, DM54LS93/DM74LS93 Jpg National Jud Semiconductor DM54LS90/DM74LS90, DM54LS92/DM74LS92, DM54LS93/DM74LS93 Decade, Divide by 12, and Binary Counters General Description Features Each o f th e s e m o n o lith ic c o u n te rs c o n ta in s fo u r m a s te r­

DM54

Abstract: DM74
Contextual Info: DM54L54/DM74L54 National ÆjA Semiconductor DM54L54/DM74L54 4-Wide AND-OR-INVERT Gates General Description Absolute Maximum Ratings Note d This device con tains a com bination of gates w hich per­ form s the logic AND-OR-INVERT function. Supply V oltage

DM54

Abstract: DM74
Contextual Info: DM54L78/DM74L78 National SiA Semiconductor DM54L78/DM74L78 Dual Master-Slave J*K Flip-Flops with Preset, Common Clear, Common Clock, and Complementary Outputs General Description Absolute Maximum Ratings Note 1 This device con tains tw o m aster-slave J-K flip-ftops

74L164

Abstract: 54L164 DM54 DM74
Contextual Info: DM54L164A/DM74L164A National Ææ Semiconductor DM54L164A/ DM74L164A 8-Bit Serial In/Parallel Out Shift Registers General Description These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input in­

DM54

Abstract: DM74
Contextual Info: DM54L30/DM74L30 National £jm Semiconductor DM54L30/DM74L30 8-Input NAND Gate General Description Absolute Maximum Ratings Note d T h is d e vice c o n ta in s a s in g le g a te w h ic h p e rfo rm s th e lo g ic N A N D fu n c tio n . S u p p ly V o lta g e

DM7413N

Abstract: DM54 DM74 DM7413
Contextual Info: DM5413/DM7413 HQ National Sim Semiconductor DM5413/DM7413 Dual 4-Input NAND Gates with Schmitt Trigger Inputs General Description Absolute Maximum Ratings Note d This device con tains tw o independent gates each of w hich perform s the logic NAND fun ction. Each input

DM74L75A

Abstract: 74l75 DM54 DM54L75A DM74
Contextual Info: DNI54L75A/DM74L75A National ÀjA Semiconductor DM54L75A/DM74L75A Quad Latches General Description Absolute Maximum Ratings Note n These latche s are ide a lly su ited fo r use a s te m p o ra ry s to r­ age fo r binary inform ation betw een p roce ssin g units and

DM54S08

Abstract: DM74L08 DM54 DM54L08 DM74 DM74S08
Contextual Info: DM54L08/DM74L08 National SiA Semiconductor DM54L08/DM74L08 Quad 2-Input AND Gates General Description Absolute Maximum Ratings Note 1 This device contains four independent gates each of w hich perform s the logic AND function. Supply Voltage Input Voltage

62882

Abstract: 74AS151
Contextual Info: DM54AS1511DM74AS151 PRELIMINARY National 4lA Semiconductor DM54AS151 /DM74AS151 8-Line to 1 •Line Data Selector/Multiplexer General Description Absolute Maximum Ratings Noted This Data Selector/M uttiplexer contains full on-chip decod­ ing to select one-of-eight data sources as a result o f a

Contextual Info: 54LS20,DM54LS20,DM74LS20 54LS20 DM54LS20 DM74LS20 Dual 4-Input NAND Gates Literature Number: SNOS291A 54LS20 DM54LS20 DM74LS20 Dual 4-Input NAND Gates General Description Features This device contains two independent gates each of which performs the logic NAND function

Contextual Info: DM54ALS677/ DM74ALS677, DM54ALS678/ DM74ALS678 PRELIMINARY National ÉjA Semiconductor DM54ALS677/ DM74ALS677, DM54ALS678/ DM74ALS678 Address Comparators General Description Features The ’ALS677 and ’ALS678 address com parators sim plify addressing of memory boards and/or other peripheral

TLO6

Abstract: 74S242 74S243 S243 74S242N
Contextual Info: DM 54S242/ DM 74S242. DM54S243/DM74S243 Quadruple Bus Transceivers General Description Absolute Maximum Ratings Note d These four data line transceivers are designed for asyn­ chronous two-way communications between data buses. They can be used to drive terminated lines down to 133

400S

Abstract: DM54 DM74 DM7454
Contextual Info: DM5454/DM7454 National äLA Semiconductor DM5454/DM7454 4-Wide 2-Input AND-OR-INVERT Gates General Description Absolute Maximum Ratings Note 1 This device con tains a com binatio n of gates w hich perform s the logic AND-OR-INVERT fun ction. Supply V oltage

pin diagram of 74153

Abstract: multiplexor 74153 74253 pin diagram multiplexer 74153 TTL 74153 74S253 DM54 DM54153 DM54253 DM74
Contextual Info: DM54253/DM74253 gga National ÆüâSemiconductor DM54253/DM74253 TRI-STATE Dual 1 of 4 Line Data Selectors/Multiplexers General Description T h is d evice is a TRI-STATE ve rsio n o f th e very p o p u la r D M 54153 DM7214 d a ta s e le c to rs /m u ltip le x e rs . It c o n ­

74AS131

Abstract: H 349
Contextual Info: DM54AS131/DM74AS131 National JutSemiconductor DM54AS1311DM74AS131 3-to-8 Line Decoders/Demultiplexers with Address Registers General Description Features The DM54/74AS131 is a 3-to-8 line decoder/dem ultiplexer with registers on the three address inputs. When the clock

74155 demultiplexer

Abstract: 74155 demultiplexer pin diagram and function table CI 74156 74155N decoder 74156 CI 74155 74155 demultiplexer function table ma 6197 74155 PIN DIAGRAM r6549
Contextual Info: DM54155/DM74155, DM54156/DM74156 National J tii Semiconductor DM54155/DM74155, DM54156/DM74156 Dual 2-Line to 4-Line Decoders/Demultiplexers General Description These TTL c irc u its fe a tu re dual 1*line-to-4-line d e m u lti­ ple xe rs w ith individual stro b e s and com m on bin a ry-a dd re ss

6308-1

Contextual Info: DM54AS353/ DM74AS353 PRELIMINARY National Semiconductor DM54AS353/DM74AS353 TRI-STATE* Dual 4-Line to 1-Line Data Selector/Multiplexer Pin and functional com patible w ith LS and Schottky Family counterpart. Improved ou tput transient handling capability.

74LS386N

Abstract: 54LS386 74LS386 DM54 DM74 DM74LS386 54LS386J
Contextual Info: DM54LS386/DM74LS386 National Sim Semiconductor DM54LS386/DM74LS386 Quad 2-Input Exclusive-OR Gates General Description Absolute Maximum Ratings Note 1 This device contains four independent gates each of w hich performs the logic exclusive-OR function. Supply Voltage

DM74S22

Contextual Info: DM54S22/DM74S22 National Semiconductor DM54S22/DM74S22 Dual 4-Input NAND Gates with Open-Collector Outputs General Description Absolute Maximum Ratings Note 1 T h is d e v ic e c o n ta in s fo u r in d e p e n d e n t g a te s e a ch o f w h ic h p e rfo rm s th e lo g ic N A N D fu n c tio n . T h e ope n c o lle c to r o u tp u ts re q u ire e x te rn a l p u ll-u p re s is to rs fo r

54LS368

Abstract: 54LS368A 54LS368ADMQB 54LS368AFMQB 54LS368ALMQB DM54LS368A DM54LS368AJ DM54LS368AW DM74LS368A DM74LS368AM
Contextual Info: 54LS368A DM54LS368A DM74LS368A Hex TRI-STATE Inverting Buffers General Description This device contains six independent gates each of which performs an inverting buffer function The outputs have the TRI-STATE feature When enabled the outputs exhibit the low impedance characteristics of a standard LS output with