74LS386 Search Results

74LS386

Abstract: SN54/74LS386 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS386DC
Contextual Info: SN54/74LS386 QUAD 2-INPUT EXCLUSIVE-OR GATE QUAD 2-INPUT EXCLUSIVE-OR GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 1 2 3 4 5 6 7 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

Contextual Info: LS TTL DN74LS Series 74LS386 74LS386 N>74LS3?£ Quad 2 -input E xclu sive OR G ates • Description P-1 D N 74LS386 contains four 2-input exclusive O R gate circuits. ■ Features • • • • Low pow er consum ption Pd = 30.5m W typical High speed ( tpd = 1 In s typical)

74LS386

Abstract: N74LS386F N74LS386N S54LS386F S54LS386W
Contextual Info: 54LS/74LS386 ORDERING CODE PACKAGES PIN CONFIGURATION See Section 9 for further Package and Ordering Information C O M M E R C IA L RANGES ± 5%' t A = ° ° c *0 *70°c PIN CO N F. VCC = s v P lastic DIP Fig. A 74LS386N C eram ic DIP Fig. A N 74LS386F

74LS574

Abstract: ttl 74LS173 74ls399 93L38 ttl 74165 ttl 7491 54LS 74LS266 ttl 74173 74LS568
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D93 54LS/74LS379 D94 9386, 74LS266, 54LS/74LS386 D95 54LS/74LS398 Vcc 1 4 5 12 13 4 5 7 6 14 15 17 16 lOa Ila lob lib lo c lie lod lid r ei fi r E5i r?i n S CP Qa Qb 2 GND Vcc = Pin 20 GND = Pin 10 Vcc = Pin 16

74LS386 EQUIVALENT

Contextual Info: ! LS TTL DN74LS Series 74LS386 74LS386 Quad 2 -input E xclu sive OR G ates • Description P-1 DN 74LS386 contains four 2-input exclusive O R gate circuits. ■ Features • • • • Low pow er consum ption P,j = 30.5m W typical High speed ( t pd = 1 In s typical)

74LS568

Abstract: TTL 74121 74167 74LSS02 74ls399 54LS 74LS266 9602 Fairchild 9602 74123 74ls379
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D93 54LS/74LS379 D94 9386, 74LS266, 54LS/74LS386 D95 54LS/74LS398 Vcc 1 4 5 12 13 4 5 7 6 14 15 17 16 lOa Ila lo b lib lo c lie lo d lid r ei f i r E5i r?i n S CP Qa Qb 2 GND Vcc = Pin 20 GND = Pin 10 Vcc = Pin 16

74L86

Contextual Info: TYPES SN54LS386A, 74LS386A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES MARCH 1974 — REVISED DECEMBER 1983 SN 54LS386A Electr sally Identical to SN 54LS86A/SN74LS86A J OR W PACKAG E SN 74LS386A D, J OR N PACKAG E T O P V IE W Mechanically Identical to SN 54L86/S N 74L86

74LS386

Contextual Info: 54LS/74LS386 ORDERING CODE PIN C O N F. PACKAGES PIN CONFIGURATION See Section 9 for further Package and Ordering Information M ILITA R Y RANGES C O M M E R C IA L RANGES VCC = 5V 1 5%; Ta = 0°C lo *70°C Plastic DIP Fig. A 74LS386N Ceramic DIP Fig. A

Contextual Info: M M O T O R O L A SN54/74LS386 QUAD 2-INPUT EXCLUSIVE-OR GATE Q UAD 2-IN P U T EX CLUSIVE-O R GATE LOW POWER SCHOTTKY Vcc nn rïïi ri nri hïïi m m _ i> = i k i - J SUFFIX CERAMIC CASE 632-08 Ll I Ll I Ll I Lil Ll I Ll I Ll I GND n s u f f ix m m n i

d92 02

Abstract: D174 74LSS02 74ls175 pin diagram 74LS164 74LS266 D172 ttl 74175 74LS164 PIN DIAGRAM 74LS194
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D93 54LS/74LS379 D94 9386, 74LS266, 54LS/74LS386 D95 54LS/74LS398 r ei fi r E5i r?i n Vcc 1 4 5 12 13 4 5 7 6 14 15 17 16 lOa I la lo b lib lo c lie lo d lid S CP Qa Qb 2 GND Vcc = Pin 20 GND = Pin 10 Vcc = Pin 16

7411 pin diagram

Abstract: TTL 7408 DS 7409 74LS574 CI 7408 7407 connection diagram 74LS386 TTL 7408 DIAGRAMS 74LS08 PIN CI 74LS08
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D93 54LS/74LS379 D94 9386, 74LS266, 54LS/74LS386 D95 54LS/74LS398 r ei fi r E5i r?i n Vcc 1 4 5 12 13 4 5 7 6 14 15 17 16 lOa Ila lo b lib lo c lie lo d lid S CP Qa Qb 2 GND Vcc = Pin 20 GND = Pin 10 Vcc = Pin 16

DN74LS386

Contextual Info: 74LS386 LS TTL DN74LS Series 74LS386 To74 LS 3 W » Quad 2 -input E xclu sive OR G ates • Description D N 74LS386 contains four 2 -input exclusive O R gate circuits. ■ Features • • • • ■ Low pow er co n sum ption P j = 30.5m W typical

DN74LS386

Contextual Info: 74LS386 LS TTL DN74LS Series 74LS386 Quad 2 - input E xclu sive OR G ates • Description P-1 D N 74LS386 contains four 2-input exclusive O R gate circuits. ■ Features • • • • Low pow er consum ption P,j = 30.5mW typical High speed ( t pd = 1 In s typical)

751A-02

Abstract: 74LS386 64606 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 751A02 truth table NOT gate 74
Contextual Info: SN54/74LS386 QUAD 2-INPUT EXCLUSIVE-OR GATE QUAD 2-INPUT EXCLUSIVE-OR GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 1 2 3 4 5 6 7 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

74LS386

Contextual Info: MOTOROLA SN54/74LS386 QUAD 2-INPUT EXCLUSIVE-OR GATE QUAD 2-INPUT EXCLUSIVE-OR GATE LOW POWER SCHOTTKY Vcc [»I nu [ïïi nyi pjfl m ffl - Ì P KÌLlI Lil Lil L±J Lil L±J J SUFFIX CERAMIC CASE 632-08 \j J GND n s u f f ix J f f l P C ÏÏS E D SUFFI soic

74LS386

Abstract: 74LS38
Contextual Info: M M OTOROLA SN54/74LS386 _ _ _ _ _ R R Fl R H R R VCC QUAD 2-INPUT EXCLUSIVE-OR GATE LÜ LiJ LiJ LJ LlI 111 LlJ LOW POWER SCHOTTKY J Suffix — Case 632-08 {Ceramic! N Suffix — Case 646-06 (Plastic) GUARANTEED OPERATING RANGES PARAMETER SYM B O L

20-PIN

Abstract: 50J2 M74LS386P
Contextual Info: MITSUBISHI LSTTLs 74LS386P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATE DESCRIPTION The M 7 4 L S 3 8 6 P is a semiconductor circuit containing four integral circuits configured into dual input exclusive OR gates. FEATURES • Capable o f withstanding high input voltages V , ^ 1 5 V

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES

ALU IC 74181

Abstract: 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 7411 3 INPUT AND gate TTL 74ls83 pin diagram of 7411 logic diagram of 7432
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 Vcc Vcc 1^1FH [iä| [vii Eòi [T| r»1 füi Fai np f i ! Föi lyi rn

Contextual Info: SfaE D • 7 ^ 2 3 7 0G4G20G T - H Z - Z - T51 ■S G TH / T 7 S C S -T H O M S O N *7# M54HC386 M74HC386 S G S- THOMSON QUAD EXCLUSIVE-OR GATE ■ HIGH SPEED tpo = 14 ns TYP.) at Vcc = 5V ■ LOW POWER DISSIPATION Ice = 1 /*A (MAX.) at Ta = 25°C ■ HIGH NOISE IMMUNITY

703C

Abstract: SN54LS386A SN74LS386A
Contextual Info: SN54LS386A, 74LS386A QUADRUPLE 2 INPUT EXCLUSIVE OR GATES SDLS171 m a r c h 1974 - SN54LS386A . . . J O R W PACKAGE 74LS386A . . . D O R N PACKAGE ITOP VIEW Electrically Identical to SN54LS86A/SN74LS86A Mechanically Identical to SN54L86/SN74L86 ia C 1

k2645

Abstract: k4005 U664B mosfet k4005 MB8719 transistor mosfet k4004 SN16880N stk5392 STR451 BC417
Contextual Info: 1 BHIAB Electronics Du som söker besvärliga IC & transistorer, börja Ditt sökande hos oss – vi har fler typer på lager än man rimlingen kan begära av ett företag Denna utgåva visar lagerartiklar men tyvärr saknas priser och viss information Men uppdatering sker kontinuerligt

74hc38

Abstract: 74HC386 LS386 54HC 74HC M54HC386 M74HC386 1513E
Contextual Info: M 54HC386 M 74HC386 SGS-THOMSON QUAD EXCLUSIVE-OR GATE HIGH SPEED tpD = 14 ns TYP. at V c c = 5V LOW POWER DISSIPATION lCc = 1 mA (MAX.) at TA = 2 5 °C HIGH NOISE IM M U NITY VniH = V n il= 2 8 % Vcc (MIN.) O U TPU T DRIVE CAPABILITY 10 LSTTL LOADS SYMM ETRICAL O U TPU T IM PEDANCE

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25