54LS Search Results

74LS169BN

Abstract: 74S169
Contextual Info: TYPES 54LS169B, SN54S168, SN54S169, SN74LS169B, SN74S168, SN74S169 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS OCTOBER 1976 —REVISED MAY 1983 S168 . . . SYNCHRONOUS UP/DOW N DECADE COUNTERS 'LS169B, 'S169 . . . SYNCHRONOUS UP/DO W N BINARY COUNTERS SN 54S 168, 5N 54LS169B, S N 54S 169 . . . J OB W PACKAGE

logic diagram of 7432

Abstract: Texas Instruments TTL 7432
Contextual Info: SN5432, SN 54LS32, SN54S32. SN7432, SN74LS32, SN74S32 QUADRUPLE 2-INPUT POSITIVE-OR GATES DECEMBER 1983-REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs • SN 5432. SN 54LS32, SN 54S 32 . . . J OR W PACKAGE

IC 7422

Abstract: 7422 74LS22D as 5422 T3228
Contextual Info: SN5422, SN 54LS22, SN54S22, S N 7422 , S N 74 LS 2 2 , SN 74S22 D U A L 4-INPUT POSITIVE N A N D G A TES W ITH O P EN C O LLEC TO R O U TPU TS DECEMBER 1983 - REVISED MARCH 19B8 Package Options Include Plastic "Small Outline” Packages, Ceramic Chip Carriers

74ls303

Abstract: 7459 IC TTL sn 7458 IC 7458 64LS 84ls IC 7459 IC 74283 sn 7457
Contextual Info: TTL MSI . TYPES SNS41S3I3. S1I74LS363 DUAL 4-LINE-TO-l-LHftf DATA SILECTOit^MULIU>LEXERS WITH 3-STATE OUTPUTS B U LLETIN NO. DL-S 781246J , O CTO BER 1976 SN 54LS 353 . . . J O R W P A C K A G E SN 74LS 353 . . . J O R N P A C K A G E T O P V |E W Inverting Versions of 54LS253, SN74LS2S3

74LS166A

Abstract: 54ls166a 54LS166
Contextual Info: SN54166, SN 54LS166A, SN74166. SN 74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS OCTOBER 1976 - REVISED MARCH 1988 S N 54166, S N 54LS 166A . . . J OR W PACKAGE S N 7416 6 . . . N PACKAGE S N 74LS 166A . . . D OR N PACKAGE • Synchronous Load • Direct Overriding Clear

IC 74LS153

Abstract: 74153 mux cd 74153 ic 74153 IC - 74LS153 74LS153 8 to 1 mux 74LS153 74153 74s153 2C011
Contextual Info: SN54153, SN 54LS153, SN 54S1S3 S N 74153, SN 74LS153, SN 74S153 DUAL 4 LINE TO 1-LINE DATA SELECTORSfM ULTIPLEXERS D E C E M B ER 1972 - R E V IS E D M A R C H 19B8 Permits Multiplexing from N lines to 1 line S N 54153, SN 5 4 LS1 5 3 , SN 5 4 S1 5 3 . . . J OR W

54LS590

Abstract: ls590 w31140
Contextual Info: TYPES 54LS590, 54LS591, SN74LS590, SN74LS591 8-BIT BINARY COUNTERS WITH OUTPUT REGISTERS D2632, JANUARY 1961 - REVISED JUNE 1983 SN 54LS590, 54LS591 . . . J OR W PACKAGE SN74LS590, SN74LS591 . . . J OR N PACKAGE 8-Bit Counter w ith Register Parallel Register Outputs

74LS357

Abstract: SC14113 31003 ha V69D ic ttl 74ls LS357
Contextual Info: TYPES 54LS354, 54LS355, 54LS356, 54LS357, SN74LS354, SN74LS355, SN74LS356, SN74LS357 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS/REGISTERS _ D 2 5 4 4 , JULY 19 7 9 -R E V IS E D APRIL 1 9 8 5 SN 54LS354, SN 54LS355 . . . J PACKAGE

LS 7475

Abstract: C4408
Contextual Info: SN5475, SN5477, 54LS75, 54LS77. SN7475, SN74LS75 4 BIT BISTABLE LATCHES MAR CH 1 9 7 4 - each latch (TOP VIEW) OUTPUTS INPUTS REVISED M A R C H 1 9 8 8 SN 5475 , SN 54LS75 . . . J OR W PACKAGE S N 7475 . . . N PACKAGE SN 74LS 75 . . . D O R N PACKAGE

SN54LS654

Contextual Info: TYPES 54LS651 THRU 54LS654 SN74LS651 THRU SN74LS654 OCTAL BUS TRANSCEIVERS AND REGISTERS 02637, JA N U A R Y ' • Bus Transceivers/Registers 19 81 - R E V IS E D DECEMBER 1983 S N 54LS ' . . . JT PACKAGE S N 74LS ' . . . D W , JT OR N T PACKAG E Independent Registers and Enables for A and

54LS466

Abstract: 74LS467 74LS465 74LS468 74ls46 81LS98 74ls466
Contextual Info: 54LS465 THRU 54LS468, SN74LS465 THRU SN74LS468 OC TAL BU FFERS W ITH 3 S T A T E OUTPUTS D 2 6 3 1 , JA N U A R Y 1981 - SN 54LS465 AND SN 54LS466 . . . J PACKAGE SN 74LS465 AND SN 74LS466 . . . DW OR N PACKAGE TOP VIEW! G1 A1 • 3-State Outputs Rated at lo L o f 12 m A and

Contextual Info: TYPES SN54194, 54LS194A, SN54S194, SN74194, SN74LS194A, SN74S194 -BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS MARCH 1974-REVISED APRIL 1985 Parallel Inputs and Outputs SN 54194, SN 54LS194A, S N 5 4 S 1 9 4 I OR W P AC K A G E S N 7 4 1 9 4 . . . J OR N P AC K A G E

Contextual Info: 54LS242, 54LS243, SN74LS242, SN74LS243 QUADRUPLE BUS TRANSCEIVERS APHIL 1985 —REVISED MARCH 198B • T w o -W a y Asynchronous C om m unication B etw een D ata Buses • P N P Inputs Reduce D -C Loading SN 54LS 242, SN 54LS 243 . . . J OR W PACKAGE SN 74LS 242. SN 74LS243 . . . D OR N PACKAGE

NV11

Abstract: multiplexers 74 LS 151
Contextual Info: SN54157, 54LS157, 54LS158. SN54S157, SN54S158, SN74157, SN74LS157, SN74LS158, SN74S157. SN74S15B QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS M AR C H 1974- - Buffered Inputs and O utputs S N 5 41 57 , S N 54LS 157, S N 54S 157. S N 5 4 L S 1 5 8 , S N 5 4 S 1 5 8 . . . J OR W PACKAGE

s433

Abstract: 74LS33 IC 7433
Contextual Info: SN 5433, SN 54LS33, SN 7433, SN 74 LS3 3 QUADRUPLE 2 INPUT POSITIVE-NOR BUFFERS WITH OPEN COLLECTOR OUTPUTS DECEMBER 1983-REVISED MARCH 19B8 S N 5 4 3 3 , S N 5 4 L S 3 3 . . J OR W PAC KA G E S N 7433 . . N P AC KA G E SN 74LS33 . . D OR N P AC KA G E TO P V IE W

SN 5477

Contextual Info: TYPES SN5475, SN5477, SN54L75, SN54L77, 54LS75, 54LS77, SN7475, SN74LS75 4-BIT BISTABLE LATCHES M A R C H 1 9 7 4 - R E V IS E D D E C E M B E R 1 9 8 3 S N 5475, SN 54LS75 . . J OR W PACKAGE S N 54L75 . . . J PACKAGE S N 7475 . . . J OR N PACKAGE SN74LS75 . , . D, J OR N PACKAGE

74LS636

Abstract: SN74LS636 SN54LS636 SN74LS637 74LS
Contextual Info: TYPES 54LS636, 54LS637, SN74LS636, SN74LS637 8-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS D 2 7 2 8 , A P R IL 1 9 8 3 , R E V IS E D D E C E M B E R 1983 SN 54LS' I PAC KA G E S N 7 4 L S ' . . . D W , J OR N P AC K A G E TO P V IE W Detects and Corrects Single-Bit Errors

74L5

Contextual Info: TYPES SN54173, 54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS OCTOBER 1976 — REVISED APRIL 1985 S N 54173, SN 54LS 173A . . . J OR W PACKAGE S N 7417 3 . . . J OR N PACKAGE S N 74L5 173A . . . D, J OR N PACKAGE 3-State Outputs Interface Directly w ith

LM 7217

Abstract: 8 bit 74166 SN54LS188 IC 74166 SN74LS166 74166 shift register IC
Contextual Info: TTL MSI TYPES SR541ft, 54LS166, SN74166, SN74LS166 8-BIT SHIFT RE6ISTERS B U LLE TIN NO. PL-S771180», OCTOBER 197 6-R E V IS E D AUGUST 1077 SN64166, SN 54LS 166. . . J OR W PACKAGE SN74166, SN74LS166 . . . J OR N PACKAGE TOP VIEW • Synchronous Load

IC 7428

Abstract: 74LS28 TTL 7428
Contextual Info: SN 5428, S N 54LS28, SN 7428, SN 74LS28 QUADRUPLE 2-INPUT POSITIVE NOR BUFFERS DECEM BER • Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs SN 5428, 54LS28 S N 7428. SN 74LS28 .

Contextual Info: Separate clock and preset Inputs BLOCK DIAGRAM (Each Flip-Flop) SPEED/PACKAGE AVAILABILITY 54LS F,W 54S A,F,W PIN CONFIGURATION 74LS A,F 74S A,F A ,F ,W DESCRIPTION PA C K A G E CLOCK 1 ^ A low level at the preset input sets the Q output high regardless of the levels at the

74LS90 pin configuration

Abstract: configuration 74ls90
Contextual Info: SPEED/PACKAGE AVAILABILITY 54 F,W S4LS F,W BLOCK DIAGRAM 54LS/74LS PIN CONFIGURATION 74 A,F 74LS A,F DESCRIPTION This monolithic counter contains four mas­ ter-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the

Contextual Info: FUNCTIONAL BLOCK DIAGRAM SPEED /PA CK AG E AVAILABILITY 54 F,W 54LS F.W PIN CONFIGURATION Each Flip-Flop 74 B,F 74LS B.F DESCRIPTION A low level at preset or clear sets or resets the outputs regardless of the levels of the other Inputs. When preset and cjear are

1 m preset

Contextual Info: SPEED/PACKAGE AVAILABILITY 54 F,W 54LS F,W PIN CONFIGURATION 74 B 74LS B B,F,W PACKAGE INFUT » .E DESCRIPTION 3 v cc r^ D A T * a This monolithic circuit is a synchronous reversible up/down counter having a complexity of 55 equivalent gates. Synchronous operation is provided by having all flip-flops clocked