LS112 Search Results

LS112

Abstract: 948F MC74HC112 MC74HCXXXD MC74HCXXXN
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC74HC112 Dual J-K Flip-Flop with Set and Reset High–Performance Silicon–Gate CMOS The MC74HC112 is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are

Contextual Info: LS1129AC Linear ICs Compander Circuit status Nom. Supp V 6.0ñ Minimum Operating Temp (øC)0 Maximum Operating Temp (øC)60 Package StyleDIP Mounting StyleT Pinout Equivalence Code16-563 # Pins16 Ckt. (Pinout) NumberLN01600563 DescriptionExpander 0-10kHz; use w/1128 Compressor

dm74 Series

Abstract: 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM
Contextual Info: LS112A National Semiconductor LS112/LS112A/LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

Contextual Info: LS73 LS76 LS107 LS112 Dual J-K Negative-Edge-Triggered Flip-Flops LS113 •Pin-for-Pin and functional equivalents to 5473, 5476, 54107, 54S112, 54S113 PIN-OUT DIAGRAMS DESCRIPTION These monolithic dual J-K flip-flops feature individual J, K, clock, and asynchronous preset and clear inputs to each

Contextual Info: LS112A National Semiconductor LS112/LS112A/LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

Contextual Info: LS1128AC Linear ICs Compander Circuit status Nom. Supp V 6.0ñ Minimum Operating Temp (øC)0 Maximum Operating Temp (øC)60 Package StyleDIP Mounting StyleT Pinout Equivalence Code16-563 # Pins16 Ckt. (Pinout) NumberLN01600563 DescriptionCompressor 0-10kHz; use w/1129 Expander

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C 7 4 H C 1 12 D ual J -K F lip -F lo p w ith S e t and R e s e t High-Performance Silicon-Gate CMOS The MC74HC112 is identical in pinout to the LS112. The device inputs are com patible with standard CMOS outputs; with pullup resistors, they are

MC54HC112

Contextual Info: MOTOROLA • SEMICONDUCTOR TECHNICAL DATA MC54/74HC112 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS The M C 54/74H C 11 2 is id entical in p in o u t to the LS112. The device in p u ts are c o m p a tib le w ith standard C M O S o u tp u ts ; w ith p u llu p resistors, th e y are c o m p a tib le

Contextual Info: AVG Semiconductors DDiT Technical Data DV74HCT112 Available Q2, 1995 DV74HC112 DV74HCT112 Dual J-K Flip-Flop with Set and Reset This device identical in pinout to the LS112. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs.

SN74LS112

Abstract: SN54LS112A SN54S112 SN74LS112A SN74S112A SN54L5112A 5S012
Contextual Info: LS112A, SN54S112, SN74 LS112A , SN74 S 112 A D U A L J-K NE GAT IVE EDGE-TRIGGERED FLIP FLO P S WITH PR ESE T AN D CLEA R SDLS011 D 2 6 6 1 , APRIL 1 9 8 2 —REVISED M A R C H 1 9 8 8 • Fully Buffered to Offer Maximum Isolation from External Disturbance

Contextual Info: MC74HC112A Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

rdn 100 n 20 550

Abstract: LS112AN MS-012-AB 74ALS 74ALS112A N74ALS112AD N74ALS112AN SOL-24 55120 LS112AD
Contextual Info: S ig n etics 7 4 LS112A F lip -F lo p Dual J-K Negative Edge-triggered Flip-Flop Preliminary Specification ALS Products DESCRIPTION The 74A LS112A, Dual N e g a tiv e Edge- T r ig g e r e d J K -T y p e F lip -F lo p , fe a tu r e s in d i­ v id u a l J, K, C lo c k C P n , S e t ( S D) a n d R e s e t

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C74HC112 Dual J -K Flip-Flop w ith Set and Reset High-Performance Silicon-Gate CMOS N SUFFIX PLASTIC PACKAGE CASE 648-08 The MC74HC112 is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are

LS107

Abstract: LS112 LS76 LS113 54S112 54S113 LS73 raytheon 74
Contextual Info: LS73 LS76 LS107 LS112 Dual J-K Negative-Edge-Triggered Flip-Flops _ LS113 •Pin-for-Pin and functional equivalents to 5473, 5476, 54107, 54S112, 54S113 P IN -O U T D IA G R A M S DESCRIPTION Th e se m o n o lith ic dual J -K flip -flo p s fe a tu re in d iv id u a l J, K ,

74HC112A

Abstract: LS112 948F MC74HC112AN hc112a
Contextual Info: MC74HC112A Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

IC 74HC112

Abstract: 74HC112 pin diagram motorola 5118 setup 74HC112A 74HC112
Contextual Info: MOTOROLA SC {LOGIC} DE D b3t.7SSS GDftDlflE 4 |~~ -01 MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC112 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS The MC54/74HC112 is identical in pinout to the LS112. The device inputs are

LS112

Contextual Info: MC74HC112A Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

Contextual Info: LS112A, LS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FUP-FLOPS WITH CLEAR AND PRESET 02661, A PRIL 1982 - REVISED MAY 1986 • Fully Buffered to Offer Maximum Isolation from External Disturbance • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers,

74HC4096

Abstract: EQUIVALENT TIMER IC WITH CD 4060 rs flip-flop IC 7400 C4050A shiftregister PIPO C148A LS 7476 L1AA C4051A LS294
Contextual Info: Selection Guide C2MOS Logic TC74HC/HCT Series 2. High Speed CMOS Selection Guide GATE NAND HCOOA NOR AND OR INVERTER, BUFFER EXCLUSIVE OR/NOR SC HM ITT TRIGGER HC02A HC08A H C31A H C04A H C86A H C14A H C51A H C4049A M ULTI FUNCTION LEVEL SHIFTER HCTOOA HCT02A

c4554

Abstract: C4581 c4072 C4549 C4015 c4632 C4510 C4014 c4582 C4063
Contextual Info: LC9100, 92000 Series No.2723A J SA\YO A k O verview The LC9100, 92000 series are semicustom LSIs especially suited to <Jéyéìop l h ^ s e r ^ q u e s t é ^ l .S l in a short period of time and at a low cost. The LC9100, 92000 series provide 17 types of m aster chip having

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

4027B

Abstract: 4013B hc374 HC-377 HC76 flip-flop HC-107 4027B equivalent hc175 HCT74
Contextual Info: SELECTION GUIDE FLIP-FLOP Type Number M54/74 Functional Equivalent LSTTL 54/74 Function Suggested Alternative LS 54/74 4000B Functional Equivalent CMOS 4000B Package DIP LS73 LS74 LS74 LS76 LS107 4027B 4013B 4013B 4027B 4027B 14 14 14 16 14 Dual J-K FLIP-FLOP with Preset and Clear

Contextual Info: SG60R4 Schottky TTL • Over 180 LS Devices • ALS • FAST TOTAL TTL COMMITMENT «TOTAL • TTL Compatible Macrocell Arrays • RAMs • PROMs General Information TTL in Perspective proved speed — p o w e r product co m p ared to LS as a result o f ad vanced M O S A IC oxide isolated processing.