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Catalog Datasheet	Type	Document Tags	PDF
ANIC Abstract: LS112 S125 DC74HC112 Contextual Info: AVG Semiconductors _ DPP Technical Data DV74HCT112 Available Q2. 1995 DV74HC112 DV74HCT112 Dual J-K Flip-Flop with Set and Reset This device identical in pinout to the LS 1 12. Each flip-flop is negative-edge clocked and has active-low asynchronous Set	OCR Scan	dv74hct112 ls112 dv74hc112 avg-003 +5avg-004 1-800-avg-semi dc74hc112 anic s125	PDF
Contextual Info: AVG Semiconductors DDiT Technical Data DV74HCT112 Available Q2, 1995 DV74HC112 DV74HCT112 Dual J-K Flip-Flop with Set and Reset This device identical in pinout to the LS112. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs.	OCR Scan	dv74hct112 dv74hc112 ls112 avg-003 +3avg-004 1-800-avg-semi dc74hc112	PDF

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ANIC

Abstract: LS112 S125 DC74HC112
Contextual Info: AVG Semiconductors _ DPP Technical Data DV74HCT112 Available Q2. 1995 DV74HC112 DV74HCT112 Dual J-K Flip-Flop with Set and Reset This device identical in pinout to the LS 1 12. Each flip-flop is negative-edge clocked and has active-low asynchronous Set

OCR Scan

dv74hct112 ls112 dv74hc112 avg-003 +5

PDF

Contextual Info: AVG Semiconductors DDiT Technical Data DV74HCT112 Available Q2, 1995 DV74HC112 DV74HCT112 Dual J-K Flip-Flop with Set and Reset This device identical in pinout to the LS112. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs.

OCR Scan

dv74hct112 dv74hc112 ls112 avg-003 +3

PDF