| SN74LS112A |  | Motorola | DUAL JK NEGATIVE EDGE-TIGGERED FLIP-FLOP | Original | PDF | 149.98KB | 4 | 
| SN74LS112A |  | Texas Instruments | DUAL J-K NEGATIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | Original | PDF | 309.89KB | 9 | 
| SN74LS112A |  | Texas Instruments | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | Original | PDF | 712.54KB | 17 | 
| SN74LS112AD |  | Motorola | Dual Negative Edge Triggered JK Flip-Flop with Preset and Clear | Original | PDF | 49.35KB | 2 | 
| SN74LS112AD |  | Motorola | Dual JK negative edge-triggered flip-flop | Original | PDF | 149.97KB | 4 | 
| SN74LS112AD |  | Texas Instruments | SN74LS112 - Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 | Original | PDF | 1.34MB | 19 | 
| SN74LS112AD |  | Texas Instruments | Dual J-K Negative-Edge-Triggered Flip-Flop with Preset and Clear | Original | PDF | 309.88KB | 9 | 
| SN74LS112AD |  | Texas Instruments | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 | Original | PDF | 864.89KB | 20 | 
| SN74LS112AD |  | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | PDF | 34.3KB | 1 | 
| SN74LS112AD |  | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | PDF | 34.3KB | 1 | 
| SN74LS112AD |  | Texas Instruments | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | Scan | PDF | 138.72KB | 5 | 
| SN74LS112ADE4 |  | Texas Instruments | SN74LS112 - Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 | Original | PDF | 1.34MB | 19 | 
| SN74LS112ADE4 |  | Texas Instruments | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET and CLEAR | Original | PDF | 712.66KB | 17 | 
| SN74LS112ADE4 |  | Texas Instruments | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 | Original | PDF | 864.89KB | 20 | 
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| SN74LS112ADG4 |  | Texas Instruments | SN74LS112 - Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 | Original | PDF | 1.34MB | 19 | 
| SN74LS112ADG4 |  | Texas Instruments | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 | Original | PDF | 864.89KB | 20 | 
| SN74LS112ADR |  | Texas Instruments | SN74LS112 - Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 | Original | PDF | 1.34MB | 19 | 
| SN74LS112ADR |  | Texas Instruments | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET | Original | PDF | 309.88KB | 9 | 
| SN74LS112ADR |  | Texas Instruments | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 | Original | PDF | 864.89KB | 20 | 
| SN74LS112ADR2 |  | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | PDF | 34.3KB | 1 |