IDD3P Search Results

Contextual Info: 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date 1.0 First Version Release Dec. 2004 1.1 1. Corrected PIN ASSIGNMENT A12 to NC Jan. 2005 1.2 1. Changed IDD3P and IDD3PS 3mA to 5mA

Contextual Info: 128Mx64 bits Unbuffered DDR SO-DIMM HYMD512M646B L F8-J/M/K/H/L Document Title 128Mx64 bits Unbuffered DDR SO-DIMM Revision History No. History Draft Date 0.1 Initial Draft Jan. 2004 0.2 IDD3P Value Adjusted from 216 to 192 [mA] at Page 9 Apr. 2004 Remark

HY57V281620ELT

Abstract: HY57V281620ET
Contextual Info: 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date 1.0 First Version Release Dec. 2004 1.1 1. Corrected PIN ASSIGNMENT A12 to NC Jan. 2005 1.2 1. Changed IDD3P and IDD3PS 3mA to 5mA

DDR200

Abstract: DDR266 DDR266A DDR266B DDR333
Contextual Info: 128Mx64 bits Unbuffered DDR SO-DIMM HYMD512M646B L F8-J/M/K/H/L Document Title 128Mx64 bits Unbuffered DDR SO-DIMM Revision History No. History Draft Date 0.1 Initial Draft Jan. 2004 0.2 IDD3P Value Adjusted from 216 to 192 [mA] at Page 9 Apr. 2004 0.3 Reflected a “notational” change in module thickness on page 17 - Not Real ! -

K4H560838D-TCC4

Abstract: K4H560838D-TCCC DDR333 DDR400 K4H561638D-TCC4 K4H561638D-TCCC
Contextual Info: DDR SDRAM 256Mb D-die x8, x16 DDR SDRAM 256Mb D-die DDR400 SDRAM Specification Revision 1.1 Rev. 1.1 Feb. 2003 DDR SDRAM 256Mb D-die (x8, x16) DDR SDRAM 256Mb D-die Revision History Revison 0.0 (June. 2002) 1. First release Revison 0.1 (Aug. 2002) - Changed IDD3P value from 40mA to 55m

hy57v281620etp

Abstract: 35A11 HY57V281620ELT HY57V281620ET
Contextual Info: 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date 1.0 First Version Release Dec. 2004 1.1 1. Corrected PIN ASSIGNMENT A12 to NC Jan. 2005 1.2 1. Changed IDD3P and IDD3PS 3mA to 5mA

Contextual Info: DDR SDRAM 256Mb D-die x8, x16 DDR SDRAM 256Mb D-die DDR400 SDRAM Specification Revision 1.0 Rev. 1.0 Feb. 2003 DDR SDRAM 256Mb D-die (x8, x16) DDR SDRAM 256Mb D-die Revision History Revison 0.0 (June. 2002) 1. First release Revison 0.1 (Aug. 2002) - Changed IDD3P value from 40mA to 55m

Contextual Info: 240PIN DDR2 667 Unbuffered DIMM 1GB With 64Mx8 CL5 TS128MLQ64V6J Description Placement The TS128MLQ64V6J is a 128M x 64bits DDR2-667 Unbuffered DIMM. The TS128MLQ64V6J consists of 16pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 240-pin

Contextual Info: 240PIN DDR2 533 Registered DIMM 1024MB With 64Mx8 CL4 TS128MQR72V5J Placement Description The TS128MQR72V5J is a 128M x 72bits DDR2-533 Registered DIMM. The TS128MQR72V5J consists of 18 pcs 64Mx8 bits DDR2 SDRAMs in 60 ball FBGA package, 2 pcs register in 96 ball uBGA package, 1 pcs

Contextual Info: 200PIN DDR2 400 SO-DIMM 256MB With 32Mx16 CL3 TS32MSQ64V4M Description Placement The TS32MSQ64V4M is a 32M x 64bits DDR2-400 SO-DIMM. The TS32MSQ64V4M consists of 4pcs 32Mx16its DDR2 SDRAMs in 84 ball FBGA packages and a 2048 bits serial EEPROM on a 200-pin printed

Contextual Info: 214PIN DDR2 533 Micro-DIMM 256MB With 32Mx16 CL4 TS32MMQ64V5M Description Placement The TS32MMQ64V5M is a 32M x 64bits DDR2-533 J Micro-DIMM. The TS32MMQ64V5M consists of 4pcs 32Mx16bits DDR2 SDRAMs in 84 ball FBGA packages and a 2048 bits serial EEPROM on printed circuit board

Contextual Info: 240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J Description Placement The TS64MLQ64V8J is a 64M x 64bits DDR2-800 Unbuffered DIMM. The TS64MLQ64V8J consists of 8 pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 240-pin printed

Contextual Info: 184PIN DDR333 Unbuffered DIMM 1024MB With 64Mx8 CL2.5 TS128MLD64V3J Description Placement The TS128MLD64V3J is a 64Mx64bits Double Data Rate SDRAM high-density Module for DDR333. The TS128MLD64V3J consists of 16pcs CMOS 64Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP-II 400mil

Contextual Info: 240PIN DDR2 800 Unbuffered DIMM 1GB With 64Mx8 CL5 TS128MLQ64V8J Description Placement The TS128MLQ64V8J is a 128M x 64bits DDR2-800 Unbuffered DIMM. The TS128MLQ64V8J consists of 16pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 240-pin

SM81600E

Abstract: IS42SM16800E IS42SM81600E IS42SM16800E-7TLI IS42SM32400E IS42SM32400E-7T IS42SM16800E-7BLI
Contextual Info: IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E 16Mx8, 8Mx16, 4Mx32 128Mb Mobile Synchronous DRAM APRIL 2011 DESCRIPTION FEATURES • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access and precharge

IS43DR81280B

Abstract: IS46DR16640B IS43DR16640B-25DBL IS46DR16640B-3DBLA IS43DR16640B IS43DR16640B-3DBL
Contextual Info: IS43/46DR81280B/L, IS43/46DR16640B/L PRELMINARY INFORMATION AUGUST 2012 1Gb x8, x16 DDR2 SDRAM FEATURES •               Clock frequency up to 400MHz 8 internal banks for concurrent operation

CMS3216LAF

Abstract: CMS3216LAG CMS3216LAH
Contextual Info: CMS3216LAx-75xx 32M 2Mx16 Low Power SDRAM Revision 0.2 January, 2007 Rev0.2, Jan. 2007 CMS3216LAx-75xx Document Title 32M(2Mx16) Low Power SDRAM Revision History Revision No. History Draft date Remark 0.0 Initial Draft Mar.3rd, 2005 Preliminary 0.1 Add H(Pb-Free & Halogen Free) descriptions

Contextual Info: CMS4A16LAx–75Ex 128M 8Mx16 Low Power SDRAM Revision 0.5 May. 2007 Rev. 0.5, May. ‘07 CMS4A16LAx–75Ex Document Title 128M(8Mx16) Low Power SDRAM Revision History Revision No. History Draft date Remark Preliminary 0.0 Initial Draft Apr.25th, 2005 0.1

W9825G6JH

Abstract: A-04 w9825g6jh-6l w9825g6jh-6
Contextual Info: W9825G6JH 4 M  4 BANKS  16 BITS SDRAM Table of Contents1. GENERAL DESCRIPTION . 3 2. FEATURES . 3

Contextual Info: Rev. 1.21. Apr. 2012 M474B5173BH0 M474B1G73BH0 204pin Unbuffered ECC SODIMM based on 4Gb B-die 78FBGA with Lead-Free & Halogen-Free RoHS compliant datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.

W9425G6JH

Contextual Info: W9425G6JH 4 M  4 BANKS  16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

Contextual Info: 4GB x72, ECC, DR 240-Pin 1.35V DDR3L VLP RDIMM Features 1.35V DDR3L SDRAM VLP RDIMM MT18KDF51272PDZ – 4GB Features Figure 1: 240-Pin RDIMM (MO-269 R/C L) • DDR3L functionality and operations supported as defined in the component data sheet • 240-pin, very low profile, 18.75mm, registered dual

Contextual Info: 8GB x72, ECC, SR 240-Pin DDR3 RDIMM Features DDR3 SDRAM RDIMM MT18JSF1G72PZ – 8GB Features Figure 1: 240-Pin RDIMM (MO-269 R/C C2) • DDR3 functionality and operations supported as per the component data sheet • 240-pin, registered dual in-line memory module

Contextual Info: M2S1G64CBH4B5P / M2S2G64CB88B5N / M2S4G64CB8HB5N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SO-DIMM Based on DDR3-1066/1333/1600 128Mx16 1GB / 256Mx8 (2GB) / 256Mx8 (4GB) SDRAM B-Die Features •Performance: