RT54SX32S Search Results

AC149

Abstract: CQFP 256 PIN actel RT54SX RT54SX-S 149-IO 208-Pin CQFP
Contextual Info: Application Note AC149 Design Migration from the RT54SX32 to the RT54SX32S Device Actel’s RT54SX-S family of FPGAs is designed specifically for space applications. Although architecturally related to the earlier radtolerant RT54SX family, there are a few

CQFP 256 PIN actel

Abstract: 208-Pin CQFP RT54SX32 RT54SX32S
Contextual Info: Technical Brief Design Migration from the RT54SX32 to the RT54SX32S Device Actel’s RT54SX-S family of FPGAs is designed specifically for space applications. Although architecturally related to the earlier radtolerant RT54SX family, there are a few differences. This technical brief is intended to help

verilog code for fir filter using DA

Abstract: A3P1500 vhdl code of 32bit floating point adder digital FIR Filter verilog code digital FIR Filter VHDL code fir vhdl code FIR Filter verilog code vhdl code for floating point adder IQ GENERATOR CODE WITH VHDL RTAX2000
Contextual Info: CoreFIR Finite Impulse Response FIR Filter Generator Product Summary Core Deliverables • Intended Use • – Finite Impulse Response (FIR) Filter for Actel FPGAs • Key Features • – • Self-Checking – Executable Tests Generated Output against Algorithm

1553b VHDL

Abstract: Actel 1553b fpga 1553B transistor BC 584 MIL-STD-1553B FPGA RT MIL-STD-1553B ACTEL FPGA manchester verilog decoder vhdl code manchester encoder mil-std-1553b SPECIFICATION transistor BC 490
Contextual Info: Core1553BBC MIL-STD-1553B Bus Controller Product Summary • Intended Use • 1553B Bus Controller BC • DMA Backend Interface to External Memory Synthesis and Simulation Support Key Features • • • • • • Supports MIL-STD-1553B Interfaces to External RAM

HiRel a54sx72a unused

Contextual Info: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

verilog code for implementation of des

Abstract: vhdl code for DES algorithm RTAX1000S rtax1000 verilog code for des vhdl code for des decryption data encryption standard vhdl wireless encrypt
Contextual Info: Core3DES Product Summary Intended Use • Whenever Data Is Transmitted Across an Accessible Medium wires, wireless, etc. • E-Commerce Transactions, Where Dedicated Encryption/ Decryption Hardware Can Ease the Load on Servers Core Deliverables • Evaluation Version

rt54sx32su

Abstract: RTSX72 RTSX32SU RTSX72-S
Contextual Info: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs

Abstract: RT54SX72S-CQ256 RTSX32S
Contextual Info: Advanced v 0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <

Contextual Info: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

TM101

Contextual Info: Advanced v1.2.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10

HiRel a54sx72a unused

Contextual Info: Advanced v1.6 RTSX-S RadTolerant FPGAs for Space Application S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

Contextual Info: Advanced v0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <

UART 8251

Abstract: 8251 uart in vhdl code 8251 uart vhdl 8251 uart verilog code for baud rate generator vhdl code for a 9 bit parity generator verilog code for 8251 vhdl code for uart vhdl ODD parity generator A42MX09
Contextual Info: v5.1 CoreUART P ro d u ct S u m m a r y S y n t h es is a n d S im u la t io n S u p po r t I n t en d ed U se • Synthesis: Exemplar, Synplicity, Design Compiler, FPGA Compiler, FPGA Express • Basic Interface to Industry Standard UART Controllers • Embedded Systems for Sharing Data between Devices

RTAX1000S-STD

Abstract: fpga 1553B 1553b VHDL RTAX1000S V203M manchester verilog decoder MIL-STD-1553B FPGA vhdl code manchester encoder MIL-HDBK-1553A 553B
Contextual Info: v2.0 MIL-STD-1553B Bus Controller Core1553BBC Pr od uc t S um m ary S ynt he si s and S im ul ati on S uppor t In t e n d e d Us e • Synthesis: Exemplar, Synplicity, Design Compiler, FPGA Compiler, FPGA Express • 1553B Bus Controller BC • DMA Backend Interface to External Memory

RT54SX72SCQ208

Abstract: CQ208 AC195 SY-PQ208-2 A54SX72A-PQ208 ACTEL CCGA to FBGA Adapter RT54SX32SCQ208 RT54SX32S-CQ208 FG484 A54SX32APQ
Contextual Info: Application Note AC195 Prototyping for the RTSX-S Enhanced Aerospace FPGA Introduction Actel provides radiation-tolerant FPGAs for space applications. However, since the enhanced environmental properties of radiation tolerant devices are not required during prototyping, inexpensive

ESD-S3.1

Abstract: IC SEM 2005 RTSX32SU TM3015 TM3015.7 transistor N3B cmos esd sensitivity ionizer A54SX08A A54SX16A
Contextual Info: Application Note AC233 Electro-Static Discharge Introduction All electronic integrated circuit IC devices are susceptible to damage from static electricity or electrostatic discharge (ESD). While some devices can withstand thousands of volts of ESD before damage, others

54SX32A

Abstract: 54SX72A ACTEL burn-in RT54SX72SCQ208 54SX32 AX54SX72A 54sx72a burn-in AC172 RT54SX32S-CQ208 A54SX72* radiation
Contextual Info: Application Note AC172 Post-Programming Burn-In PPBI for Actel RT54SX-S and SX-A FPGAs A b s t r a ct A rc h i te c t ur e Burn-in (BI) for programmed Field Programmable Gate Arrays (FPGAs) is a growing concern in the space community. This application note addresses these concerns

ACTEL 1020B

Abstract: 1010B 40MX 42MX A54SX72A AC207 RT54SX72S RH1020 actel 1020 RT54SX-S
Contextual Info: Application Note AC207 Global Clock Networks in Actel Antifuse Devices System performance is one of the most important characteristics of a design. As a result, designers put a lot of effort into improving clock speed. Clock skew is often a limiting factor in attaining maximum

pressure sensor MATLAB program

Abstract: actel rad pressure sensor 90nm cmos RTAX250S-1000S
Contextual Info: A passion for performance. Digital and Mixed-Signal custom, semi-custom, off-the-shelf designs with Aeroflex Gaisler IP Guaranteed radiation performance QML-V, QML-Q, military, medical, industrial grades Category 1A Trusted Accreditation We connect the real

RTSX32

Abstract: voter PAR64 REQ64 RT54SX72S RT54SX-S TM1019 Cqfp256
Contextual Info: Advanced v0.2 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <

CORE8051

Abstract: vhdl code for i2c Slave 54SX A42MX16 A500K050 A54SX16 A54SX16A APA075 AX125 vhdl code for i2c register
Contextual Info: v1.0 I2C Bus Controller CoreI2C v2.0 Pr od u c t S u mm a ry In te n d e d U s e • I2C bus controller • Supports 100kbps and 400kbps modes Ke y F ea t u re s • Master Transmitter Mode - Serial Data Output through SDA while SCL Outputs the Serial Clock

vhdl code for manchester decoder

Abstract: manchester verilog decoder MIL-HDBK-1553A 1553b VHDL 1553b bu-63147 fpga 1553B SA30L Verilog implementation of a Manchester Encoder/Decoder
Contextual Info: v3.0 MIL-STD-1553B Remote Terminal Core1553BRT Pr od uc t S um m ary De vel opm en t Sy s te m In t e n d e d U s e • Complete 1553BRT Implementation, Implemented in an A54SX32A • 1553B Remote Terminal RT • DMA Backend Interface to External Memory

RTAX2000

Abstract: ProASIC3 A3P250 RTAX1000S A3P125 A54SX16A A54SX32A APA075 AX125 PAR64 RTAX250S
Contextual Info: CorePCI v5.41 Product Summary Synthesis and Simulation Support Intended Use • Most Flexible High-Performance PCI Offering – Synthesis: ExemplarTM, Synopsys DC / FPGA CompilerTM, and Synplicity® • Simulation: Vital-Compliant VHDL Simulators and OVI- Compliant Verilog Simulators

54SXA

Abstract: DF1 Pinout A54SX32A SEU RT54SX-S
Contextual Info: Application Note Prototyping for the RT54SX-S Enhanced Aerospace FPGA Actel provides radiation tolerant FPGA devices for use in Aerospace applications. However, since the enhanced environmental properties of radiation tolerant devices are not required during prototyping, an inexpensive