VOTER Search Results

sy 351

Abstract: ic 351 diode 351 teledyne hi-nil 1N4148 Teledyne Semiconductor diode SY 351 SY 351/6
Contextual Info: TSC350/351 5 8 0 PleasantStreet '.Votertown, M A 0217 2 617 9>:4-9?60 / /m M llIt ip lG X C f S O .R i* W O D ll c • Dual 4-Bit •eatures G e n e ra l D escription • V E R S A T IL E D E S IG N C O N FIG U R A T IO N Teledyne Semiconductor 350 8-Bii, end 351 Duel 4-Bit Multi­

m1 250c fuse

Abstract: at32uc3c em 234 stepper dtx 370 DTH block diagram lta 301 VT 546 Modem basic circuit diagram EIC 4021 shift registers 4050
Contextual Info: Features • High Performance, Low Power 32-bit AVR Microcontroller – – – – • • • • • • • • • • • • Compact Single-cycle RISC Instruction Set Including DSP Instruction Set Built-in Floating-Point Processing Unit FPU Read-Modify-Write Instructions and Atomic Bit Manipulation

GCM 38112

Abstract: Wifi to I2C ST ATUC3A4256S AT32UC3A3 dsp ssb modulation demodulation barcode reader using avr AT32UC3A64 ATUC3A3256 DesignWare Hi-Speed USB On-The-Go Controller AT32UC3A3256S
Contextual Info: Features • High Performance, Low Power 32-bit AVR Microcontroller • • • • • • • • • • • • – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation

energy tapping identifier wireless data acquisition

Abstract: interpolation CIC Filter iso 7811-9 sine wave pwm circuit pec 4179 Isdi cmos sensor edp 2339 ARM926EJ atmel sam4l ram schematic diagram
Contextual Info: Features • Core • • • • – ARM CortexTM-M4 running at up to 48 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set picoPower® Technology for Ultra-low Power Consumption – Active mode downto 90µA/MHz with configurable voltage scaling

SN75DP128A

Contextual Info: SN75DP128A www.ti.com. SLLS940 – NOVEMBER 2008 DisplayPort 1:2 Switch

SN75DP120

Contextual Info: SN75DP120 www.ti.com SLLSE08 – OCTOBER 2009 DisplayPort 1:1 Dual-Mode Repeater Check for Samples: SN75DP120 FEATURES 1 • • • • • DP Signal Repeater Supporting Dual-Mode DisplayPort DP1.1a DP+ Signaling Supports Data Rates up to 2.7Gbps Participates in DP Link Training to set Output

fingerprint

Abstract: processor of fingerprint system block diagram of fingerprint sensor Oxford Micro Devices Fingerprint module voter FINGERPRINTS MODULE serial communication of fingerprint module circuit diagram for fingerprint sensor fingerprints
Contextual Info: A336 Fingerprint Capture and Verification Module A336 Fingerprint Capture and Verification Module A miniature autonomous fingerprint capture and verification system suitable for being built into your products to provide biometric user identification Advance Data Sheet Summary

RC7315QF

Contextual Info: www.fairchildsemi.com RC7315 Three-State ATE Pin Electronics Driver Features Description • High output slew rate 1.8 V/ns typical • Wide output voltage range (-2.5V to +7V), and up to 9.5 Vp-p swings • Three-state/high impedance output • High repetition rate (250 MHz for ECL swings)

Contextual Info: NECES001 C P20K 0 .8 -M IC R O N NEC Electronics Inc. fpgas February 1993 Description Figure 1. CP20K FPGAs NEC Electronics Inc. and Crosspoint Solutions, Inc. have joined forces to offer to system designers an expedient way to prototype in Field Programmable Gate Arrays

RC7311QA

Contextual Info: www.fairchildsemi.com RC7311 250MHz ATE Pin Electronics Driver Features Description • High output slew rate 1.8 V/ns typical • Wide output voltage range (-3.0V to +8V), and up to 10 Vp-p swings • 250MHz minimum operation for ECL swings • Wide input common mode range for ease of interface to

SN75DP120

Contextual Info: SN75DP120 www.ti.com SLLSE08 – OCTOBER 2009 DisplayPort 1:1 Dual-Mode Repeater Check for Samples: SN75DP120 FEATURES 1 • • • • • DP Signal Repeater Supporting Dual-Mode DisplayPort DP1.1a DP+ Signaling Supports Data Rates up to 2.7Gbps Participates in DP Link Training to set Output

Contextual Info: Features • High Performance, Low Power 32-bit AVR Microcontroller • • • • • • • • • • • • – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation

Contextual Info: Features • High Performance, Low Power 32-bit AVR Microcontroller – – – – • • • • • • • • • • • • Compact Single-cycle RISC Instruction Set Including DSP Instruction Set Built-in Floating-Point Processing Unit FPU Read-Modify-Write Instructions and Atomic Bit Manipulation

RC7321QF

Contextual Info: www.fairchildsemi.com RC7321 Three-State ATE Pin Electronics Driver Features Description • High output slew rate 1.3 V/ns typical • Wide output voltage range (-2.2V to +7V), and up to 9.2 Vp-p swings • Three-state/high impedance output • High repetition rate (250 MHz for ECL swings)

Contextual Info: DeltaV SIS Product Data Sheet October 2014 – Page 1 DeltaV SIS with Electronic Marshalling DeltaV SIS with Electronic Marshalling The DeltaV SIS process safety system has the world’s first CHARMs Smart SIS Logic Solver, using the power of predictive

Synplify tmr

Abstract: CC16CE vhdl code hamming edac memory vhdl code for a grey-code counter XAPP216 voter CC16RE vhdl coding for error correction and detection algorithms vhdl code hamming RAM EDAC SEU
Contextual Info: Application Note: Virtex Series R XAPP197 v1.0 November 1, 2001 Triple Module Redundancy Design Techniques for Virtex FPGAs Author: Carl Carmichael Summary Triple Module Redundancy (TMR) combined with Single Event Upset (SEU) correction through partial reconfiguration is a powerful and effective SEU mitigation strategy. This method is only

XAPP987

Abstract: voter XAPP988 XAPP216 RAM SEU fpga radiation CREME96 Upsets XAPP779 XQR2V6000
Contextual Info: Application Note: FPGAs Single-Event Upset Mitigation Selection Guide R Author: Brendan Bridgford, Carl Carmichael, and Chen Wei Tseng XAPP987 v1.0 March 18, 2008 Summary This application note discusses different aspects of single-event upsets and recommends

SN75DP128A

Contextual Info: SN75DP128A www.ti.com. SLLS940 – NOVEMBER 2008 DisplayPort 1:2 Switch

Contextual Info: SN75DP122 www.ti.com. SLLS892A – FEBRUARY 2008 – REVISED NOVEMBER 2008 DisplayPort 1:2 Switch With Integrated TMDS Translator

HiRel a54sx72a unused

Contextual Info: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

LGA 478 SOCKET PIN LAYOUT

Abstract: RTAX2000
Contextual Info: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg

rt54sx32su

Abstract: RTSX72 RTSX32SU RTSX72-S
Contextual Info: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

Contextual Info: Advanced v0.3  RTAX-S Family FPGAs Sp e ci a l F ea t ur es f o r Sp a ce • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day • Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with

Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs

Abstract: RT54SX72S-CQ256 RTSX32S
Contextual Info: Advanced v 0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <