54SX72A Search Results

54SX32A

Abstract: 54SX72A ACTEL burn-in RT54SX72SCQ208 54SX32 AX54SX72A 54sx72a burn-in AC172 RT54SX32S-CQ208 A54SX72* radiation
Contextual Info: Application Note AC172 Post-Programming Burn-In PPBI for Actel RT54SX-S and SX-A FPGAs A b s t r a ct A rc h i te c t ur e Burn-in (BI) for programmed Field Programmable Gate Arrays (FPGAs) is a growing concern in the space community. This application note addresses these concerns

54SX72

Abstract: A54SX32APQ FBGA-484 A54SX16A THERMAL Fuse m20 tf 115 c PAR64 REQ64 A54SX08A A54SX16 A54SX32A
Contextual Info: Preliminary v1.1 SX-A Family FPGAs Leading Edge Performance • Configurable I/O Support for 3.3V/5.0V PCI, LVTTL, and TTL • Configurable Weak Resistor Pullup or Pulldown for Tri-Stated Outputs at Power Up • 250 MHz System Performance • 4ns Clock-to-Out Pin-to-Pin

54SX72

Abstract: FBGA-484 A54SX32APQ208 A54SX16A
Contextual Info: Preliminary v1.1 SX-A Family FPGAs Leading Edge Performance • Configurable I/O Support for 3.3V/5.0V PCI, LVTTL, and TTL • Configurable Weak Resistor Pullup or Pulldown for Tri-Stated Outputs at Power Up • 250 MHz System Performance • 4ns Clock-to-Out Pin-to-Pin

54SX72

Abstract: actel act1 family signal path designer
Contextual Info: Actel Getting Started User’s Guide R1-2002 Windows ® and UNIX ® Environments For more information about Actel’s products, call 888-99-ACTEL or visit our Web site at http://www.actel.com Actel Corporation • 955 East Arques Avenue • Sunnyvale, CA USA 94086

DF1 Pinout

Abstract: signal path designer BUT32
Contextual Info: Actel Getting Started User’s Guide Windows ® and UNIX ® Environments For more information about Actel’s products, call 888-99-ACTEL or visit our Web site at http://www.actel.com Actel Corporation • 955 East Arques Avenue • Sunnyvale, CA USA 94086

54SX72

Abstract: CERAMIC PIN GRID ARRAY 144 pins blown fuse A2-A20 A54SX16A
Contextual Info: A d van ced v.1 54SXA Family FPGAs Specifications Output Tristate at Powerup • 8,000 to 72,000 Available Logic Gates • 100% Resource Utilization with 100% Pin Locking • Up to 360 User-Programmable I/O Pins • 4,024 Flip-Flops • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with

cordic sine cosine generator vhdl

Abstract: cordic vhdl code for cordic algorithm vhdl code for cordic vhdl code for rotation cordic vhdl code for vector cordic verilog code for cordic verilog code for cordic algorithm cordic algorithm code in verilog vhdl code for cordic cosine and sine
Contextual Info: CoreCORDIC CORDIC RTL Generator Product Summary • – Intended Use • COordinate Rotation DIgital Computer CORDIC Rotator Function for Actel FPGAs Vector Rotation – Conversion of Polar Coordinates to Rectangular Coordinates • Vector Translation – Conversion of Rectangular

A54SX08A

Abstract: FBGA-484 LRD12 A54SX16 A54SX16A A54SX32A A54SX72A PAR64 REQ64 54SX72
Contextual Info: Æ ic te ! P r e l i m i n a r y v1 .1 - m SX-AFamily FPGAs L e a d i n g E d g e Pe r f o r m a n e e • Configurable I/O Support for 3.3V5.0VPC3, LVTTL, and TIL • 250 MHz System Performance • Configurable Wfcak Resistor Pullup or Pulldown for

54SX16A

Abstract: 54sx32 54SX0 54SX08A Signal Path Designer 54SX32A
Contextual Info: Designer Series Development System R1-2000 Release Notes This document describes the new features and enhancements of the Designer Series Development System R1-2000 release. It also contains information about discontinued features and known limitations. Supported Platforms

Contextual Info: v2.0 CorePCI Target+DMA 33/66 MHz Pr od u c t S u mm a ry • Compliant with the PCI 2.2 Specification. Intended Use Version • High-Performance PCI Target+DMA Applications This data sheet defines the functionality of Version 5.1 of the CorePCI macro. – 32/64-Bit, 66MHz, 3.3V 66MHz requires the