ACTEL Search Results

cdb 4121 e

Abstract: cdb 4121 ARMv7 Cortex-m1 verilog code AHB cortex
Contextual Info: Cortex-M1 v3.1 Handbook 2010 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 50200127-12 Release: September 2010 No part of this document may be copied or reproduced in any form or by any means without prior written consent of

A1280A VKS

Abstract: A1280A-CQ172C VKS FPGA CQFP 106 actel a1280a unused pin VKS FPGA CQFP 172 antifuse programming technology A14100A-CQ256C fpga radiation A1280A ACTEL A1280A
Contextual Info: PRELIMINARY SPACE ELECTRONICS INC. SPACE PRODUCTS RADIATION TOLERANT RAD-PAK FIELD PROGRAMMABLE GATE ARRAYS FEATURES GENERAL DESCRIPTION Radiation Characteristics Actel builds the most reliable field programmable gate arrays FPGAs in the industry, with overall antifuse reliability ratings of less than 10 failures-in-time (FITs), corresponding to a useful life of more than 40 years.

AC307

Abstract: SPARTAN 3E STARTER BOARD L262144 memory 2114 XILINX/SPARTAN 3E STARTER BOARD AFS090 generic SPI AFS-EVAL
Contextual Info: Application Note AC307 Configuring SRAM FPGAs Using Actel Fusion Introduction Due to the nature of SRAM technology, SRAM-based FPGAs are volatile and lose their configuration when powered off, so they must be reconfigured at every power-up. Hence, almost every system using SRAMbased FPGAs contains an additional nonvolatile memory, such as flash PROM or EEPROM, to store the

ACTEL FUSION AFS1500

Abstract: FlashPro3 PQ208 QN108 QN180 M1AFS1500 AFS250 rc oscillator M-LVDS
Contextual Info: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

verilog code voltage regulator

Abstract: verilog code for adc verilog code voltage regulator vhdl verilog code for amba apb bus 16bit microprocessor using vhdl simple ADC Verilog code verilog code for apb vhdl code for Clock divider for FPGA vhdl code for frequency divider APB VHDL code
Contextual Info: P ro du c t Br ie f CoreAI Product Summary Synthesis and Simulation Support Intended Use • Analog Interface Control Using a Microprocessor/ Microcontroller and an Actel FusionTM Device • Voltage, Current, and Temperature Monitoring Using a Microprocessor/Microcontroller and an

CORE8051

Abstract: FlashPro3 AES-128 FG256 PQ208 ac motor variable speed control rc oscillator
Contextual Info: Preliminary v0.4 Actel Fusion Mixed-Signal FPGA for the MicroBlade Advanced Mezzanine Card Solution Features and Benefits • Targeted to Advanced Mezzanine Card AdvancedMC Designs • Designed in Partnership with MicroBlade • 8051-Based Module Management Controller (MMC)

verilog hdl code for matrix multiplication

Abstract: vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code
Contextual Info: Application Note AC319 Using EDAC RAM for RadTolerant RTAX-S/SL and Axcelerator FPGAs Applies to EDAC Core from Libero IDE v7.2 and Newer Introduction The newest Actel designed-for-space field programmable gate array FPGA family, RTAX-S/SL, is a highperformance, high-density, antifuse-based FPGA with embedded user static RAM (SRAM). Based on the

AFS600-FG256

Abstract: zo 103 ma 75 607 A54 ZENER flashpro3 schematic mark AT0 Unipolar PC atx 400 P4 power supply diagram zener Diode B23 PQ208 QN108 QN180
Contextual Info: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

ASF600

Abstract: VHDL code of lcd display vhdl code for lcd display RTC A 250 2N2222A AC271 PN2222A LCD module in VHDL rtc 294 regulator power supply
Contextual Info: Application Note AC271 Real-Time Calendar Applications in Actel Fusion Devices Introduction The Actel Fusion Programmable System Chip is the world's first mixed-signal FPGA, integrating configurable analog, a real-time counter RTC , Flash memory blocks, and clock generation circuits—all in

764150

Abstract: YAMAICHI 132 PGA SA-PQ208
Contextual Info: fcM Socket Recommendation for Actel FPGA Packages P r o t o t y p i n g S o c k e t s R e s o l d by A c t e l These sockets have been engineered and manufactured by the respective original manufacturer. Actel resells small quantities of these sockets to Actel customers in order to

A54 ZENER

Abstract: AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM
Contextual Info: v2.0 Actel Fusion Family of Mixed-Signal FPGAs Features and Benefits In-System Programming ISP and Security High-Performance Reprogrammable Flash Technology Advanced Digital I/O • • • • • Secure ISP with 128-Bit AES via JTAG • FlashLock® to Secure FPGA Contents

actel fpga 54sx32

Abstract: 54SX32 54SX16 54SX08 066V 54SX RT54SX
Contextual Info: Application Note Power-Up and Power-Down Behavior of 54SX and RT54SX Devices I n tro du ct i on One of the key benefits of Actel’s nonvolatile antifuse FPGA technology is the ability of the devices to be live at power-up. Since no configuration PROMs are required to

AGLN250Z

Abstract: AGLN060Z Datasheet AGLN020 Datasheet AGLN060 AGLN125Z 81-Pin 23919 AGLN010
Contextual Info: April 9, 2010 Customer Alert Subject: IGLOO nano Datasheet update Dear Customer, This notice is to inform you that the IGLOO nano datasheet has been updated. The updated datasheet can be downloaded from the Actel website: http://www.actel.com/ documents/IGLOO_nano_DS.pdf.

Contextual Info: A p p l i c a t i on N o t e Design for Low Power in Actel Antifuse FPGAs As system power budgets grow tighter, the need for lower power components becomes more critical. For communications infrastructure applications, board cooling, cabinet space minimization, and system reliability all play a

BPW27

Abstract: BGG272 BGG456 BPV0272-12-09705-20ACA BPV272 BPV272-127 BPW0272-12-09705-20ACA LG1906 SE-BGG272-A Actel
Contextual Info: 7 6 5 THE DRAWINGS AND INFORMATION CONTAINED H ER E IN ARE THE E X C LU SIV E P R O P E R T Y OF ACTEL. THE INFORMATION, DRAWINGS AND D E SIG N C O N C EP T S CONTAINED H ER E IN ARE C O N FID E N T IA L /P R O P R IE T A R Y , SH ALL B E MAINTAINED IN ST R IC T C O N FID EN C E, AND SH ALL NOT B E R E L E A SE D TO ANY THIRD PARTY WITHOUT THE E X P R E S S

SL1900

Abstract: SM-13912 B446 SRPB AC150V DC150V TQ64 KS-8446
Contextual Info: 8 7 6 5 4 3 THE DRAWINGS AND INFORMATION CONTAINED H EREIN ARE THE EXCLUSIVE PRO PERTY OF ACTEL. THE INFORMATION, DRAWINGS AND DESIGN CONCEPTS CONTAINED H EREIN ARE CONFIDENTIAL/PROPRIETARY, SHALL B E MAINTAINED IN STRICT CONFIDENCE, AND SHALL NOT B E RELEASED TO ANY THIRD PARTY WITHOUT THE E X P R ES S

BPW45

Abstract: BPW45b-1270 3PW45 BGG456 Socket 456
Contextual Info: 6 7 5 2 THE DRAWINGS AND INFORMATION CONTAINED H EREIN ARE THE EXCLUSIV E P R O PE R TY OF ACTEL. THE INFORMATION, DRAWINGS AND D ESIG N CO N CEPTS CONTAINED H ER EIN ARE CO N FID EN TIA L/PRO PR IETA RY , SHALL B E MAINTAINED IN STRICT CONFIDENCE, AND SHALL NOT B E R ELEA SED TO ANY THIRD PARTY WITHOUT THE E X P R E S S

LG1152

Abstract: ag34 AF33 AL P3d ami c21 E20 L27 r33 ah16 CG1152 AH33 AK33
Contextual Info: 4 3 THE DRAWINGS AND INFORMATION CONTAINED H E R E IN ARE THE EXCLUSIVE P R O P E R T Y OF ACTEL. THE INFORMATION, DRAWINGS AND DESIGN CON CEPTS CONTAINED H EREIN ARE C O N FID E N T IA L /PRO PRIET A RY , SHALL BE MAINTAINED IN STRICT CONFIDENCE, AND SHALL NOT BE RELEASED TO ANY THIRD PARTY WITHOUT THE E X PR E SS

Contextual Info: 3 ECN NO. THE DRAWINGS AND INFORMATION CONTAINED H EREIN ARE THE EXCLUSIVE P R O PE R T Y OF ACTEL. THE INFORMATION, DRAWINGS AND DESIGN CO N CEPTS CONTAINED H EREIN ARE C O N FID E N T IA L /PRO PRIET A RY , SHALL BE MAINTAINED IN STRICT CONFIDENCE, AND SHALL NOT BE RELEASED TO ANY THIRD PARTY WITHOUT THE E X PR E SS

32X8 sram

Abstract: grid tie inverter schematics A32100DX A32140DX A32200DX A32300DX A32400DX A3265DX scratchpad memory Signal Path Designer
Contextual Info: Pr eli m i nar y 3200DX Field Programmable Gate Arrays – The System Logic Integrator Family Features General Description High Capacity The 3200DX, the first device family in Actel’s Integrator™ Series, are the first FPGAs optimized for high-speed,

10uH inductor CC TECHNOLOGIES

Abstract: APA150 -TQ1001 datasheet AX2000 ISL6528 HSOP-28 thermal Actel APA075 ax rubycon capacitor 106 35K 7 pin str for 24v 3 amp to 220 package APA600
Contextual Info: HIGH PERFORMANCE ANALOG Power Management Application Guide for Actel FPGAs Using Switchers to Power Actel FPGAs FPGAs continue to grow in density and complexity while at the same time, shrinking device geometries have enabled faster system clocks and required lower core voltages. These trends call for more

TA138

Abstract: TA280 3SB24 TA1225A 176-CPGA dece2x4
Contextual Info: ACTEL CORP Æ Ic M b?E » I • 01^24^ DDDGÔ33 TS1 ■ ACT ACT 2 Field Programmable Gate Arrays Features Description • The ACT™ 2 family represents Actel’s second generation of field programmable gate arrays FPGAs . The ACT 2 family presents a two-module architecture, consisting of C-modules and S-modules.

ALY SMD

Abstract: 5962-9096501MUC actel a1240 176-CPGA actel 1240a 1240A ST
Contextual Info: ACTEL CORP b7E D • 0 1 = 1 2 4 ^ □ □ □ □ eì3cì 3SD ■ ACT ACT 1 and ACT 2 Military Field Programmable Gate Arrays ACT 1 Features • U p to 2000 G ate A rray G ates 6000 P L D e q u iv alen t g ates • R eplaces up to 53 T T L P ackages

Applications of "XOR Gate"

Abstract: vhdl code for 4 channel dma controller ATM machine using microprocessor Controller System NIC 8 bit XOR Gates FPGA based dma controller using vhdl asynchronous fifo vhdl fpga design of dma controller using vhdl signal path designer "network interface cards"
Contextual Info: Appl i cat i o n N ot e A 155 Mbps ATM Network Interface Controller Using Actel’s New 3200DX FPGAs Given that the asynchronous transmission mode ATM peripheral market is highly competitive and time-to-market is critical, logic designers must meet shrinking design cycles.