RT54SX Search Results

actel fpga 54sx32

Abstract: 54SX32 54SX16 54SX08 066V 54SX RT54SX
Contextual Info: Application Note Power-Up and Power-Down Behavior of 54SX and RT54SX Devices I n tro du ct i on One of the key benefits of Actel’s nonvolatile antifuse FPGA technology is the ability of the devices to be live at power-up. Since no configuration PROMs are required to

HiRel a54sx72a unused

Contextual Info: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs

Abstract: RT54SX72S-CQ256 RTSX32S
Contextual Info: Advanced v 0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <

TM101

Contextual Info: Advanced v1.2.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10

Contextual Info: Advanced v0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <

RT54SX72S

Abstract: A54SX72A RT54SX-S Signal Path Designer
Contextual Info: Techni c al Br i ef Using A54SX72A and RT54SX72S Quadrant Clocks Ar ch it e c tu r al Ov er vi ew The A54SX72A and RT54SX72S devices offer four quadrant clock networks QCLK0, 1, 2, and 3 that can be driven from external points or from internal logic signals within the

A54SX72* radiation

Abstract: cg624 A54SX72A actel 1020 datasheet RT54SX72S RT54SX-S TM1019 HiRel a54sx72a unused
Contextual Info: Advanced v1.4 RT54SX-S RadTolerant FPGAs for Space Applications S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

54SX32A

Abstract: 54SX72A ACTEL burn-in RT54SX72SCQ208 54SX32 AX54SX72A 54sx72a burn-in AC172 RT54SX32S-CQ208 A54SX72* radiation
Contextual Info: Application Note AC172 Post-Programming Burn-In PPBI for Actel RT54SX-S and SX-A FPGAs A b s t r a ct A rc h i te c t ur e Burn-in (BI) for programmed Field Programmable Gate Arrays (FPGAs) is a growing concern in the space community. This application note addresses these concerns

actel fpga 54sx32

Abstract: 54SX32 54SX RT54SX antifuse fpga
Contextual Info: Application Note AC145 Power-Up and Power-Down Behavior of 54SX and RT54SX Devices I n tro du ct i on One of the key benefits of Actel’s nonvolatile antifuse FPGA technology is the ability of the devices to be live at power-up. Since no configuration PROMs are required to

actel

Abstract: A54SX32 54SX A54SX16
Contextual Info: Errata v2.0 54SX Family FPGAs RadTolerant and HiRel Errata In Table 1 on page 8, the Maximum Input Tolerance for the A54SX16 and A54SX32 devices is incorrect. Here is how the table should appear. Table 1 • Supply Voltages Devices A54SX16 A54SX32 RT54SX16

RTSX32

Abstract: voter PAR64 REQ64 RT54SX72S RT54SX-S TM1019 Cqfp256
Contextual Info: Advanced v0.2 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <

54SXA

Abstract: DF1 Pinout A54SX32A SEU RT54SX-S
Contextual Info: Application Note Prototyping for the RT54SX-S Enhanced Aerospace FPGA Actel provides radiation tolerant FPGA devices for use in Aerospace applications. However, since the enhanced environmental properties of radiation tolerant devices are not required during prototyping, an inexpensive

multiplexor

Abstract: RT54SX72S RT54SX-S A54SX72A AC169 Signal Path Designer
Contextual Info: Application Note AC169 Using A54SX72A and RT54SX72S Quadrant Clocks Ar ch it e c tu r al Ov er vi ew The A54SX72A and RT54SX72S devices offer four quadrant clock networks QCLK0, 1, 2, and 3 that can be driven from external points or from internal logic signals within the

AC149

Abstract: CQFP 256 PIN actel RT54SX RT54SX-S 149-IO 208-Pin CQFP
Contextual Info: Application Note AC149 Design Migration from the RT54SX32 to the RT54SX32S Device Actel’s RT54SX-S family of FPGAs is designed specifically for space applications. Although architecturally related to the earlier radtolerant RT54SX family, there are a few

A54SX08A

Abstract: A54SX16A A54SX32A A54SX72A RT54SX72S RT54SX-S
Contextual Info: Application Note AC158 Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications I n tro du ct i on All of Actel’s FPGAs are nonvolatile, meaning they are live at power up and do not require a configuration device. This makes Actel’s chips ideal candidates for hot-swap and

RTSX32

Abstract: RTSX32S 13B8 EX64-TQ64 12B4 10B4 A54SX72A AC160 RT54SX72S RTSX72S
Contextual Info: Application Note AC160 IEEE Standard 1149.1 JTAG in the SX/RTSX/SX-A/eX/RT54SX-S Families In t ro d u ct i o n Testing modern loaded circuit boards has become extremely expensive and very difficult to perform. The rapid development of surface-mount technology and the use of

RT54SX72S

Abstract: RT54SX-S voter PAR64 REQ64 TM1019 CQFP256
Contextual Info: Advanced v0.2 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <

C4466

Abstract: FG484 CQ256 FG144 D1425 ACTEL SI-SXA-APATQ100-A-KIT SI-SX72-ACQ256SFG484 A54SX72A C4002
Contextual Info: 0HFKDQLFDO 'UDZLQJV IRU WKH $GDSWHU %RDUG S/N Package Device Actel Part Number 1 CQ256 to FG484 For A54SX72A and RT54SX72S devices SI-SX72-ACQ256SFG484 Ironwood Electronics Part Number: CQ256 to FG484 adapter for SX32 And SX72.pdf C4002

CQFP 256 PIN actel

Abstract: 208-Pin CQFP RT54SX32 RT54SX32S
Contextual Info: Technical Brief Design Migration from the RT54SX32 to the RT54SX32S Device Actel’s RT54SX-S family of FPGAs is designed specifically for space applications. Although architecturally related to the earlier radtolerant RT54SX family, there are a few differences. This technical brief is intended to help

Contextual Info: Application Note Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications I n tro du ct i on All of Actel’s FPGAs are nonvolatile, meaning they are live at power up, and do not require a configuration device. This makes Actel’s chips ideal candidates for hot-swap and

TMS 3833

Abstract: actel package mechanical drawing DIL 8 293 133A PCP bulletin 451 qml-38535 A54SX16 A54SX16-1 7540 Group SKs smd 69
Contextual Info: REVISIONS DATE YR-MO-DA _APPROVED A Added devices 03 and 04, editorial changes to table I and the appropriate paragraphs throughout the document. Added figures for bond pad locations for device 03.

40B5

Abstract: 42B2 RT54SX-S TQ100
Contextual Info: v4.1 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)

verilog code for fir filter using DA

Abstract: A3P1500 vhdl code of 32bit floating point adder digital FIR Filter verilog code digital FIR Filter VHDL code fir vhdl code FIR Filter verilog code vhdl code for floating point adder IQ GENERATOR CODE WITH VHDL RTAX2000
Contextual Info: CoreFIR Finite Impulse Response FIR Filter Generator Product Summary Core Deliverables • Intended Use • – Finite Impulse Response (FIR) Filter for Actel FPGAs • Key Features • – • Self-Checking – Executable Tests Generated Output against Algorithm

1553b VHDL

Abstract: Actel 1553b fpga 1553B transistor BC 584 MIL-STD-1553B FPGA RT MIL-STD-1553B ACTEL FPGA manchester verilog decoder vhdl code manchester encoder mil-std-1553b SPECIFICATION transistor BC 490
Contextual Info: Core1553BBC MIL-STD-1553B Bus Controller Product Summary • Intended Use • 1553B Bus Controller BC • DMA Backend Interface to External Memory Synthesis and Simulation Support Key Features • • • • • • Supports MIL-STD-1553B Interfaces to External RAM