A54SX72A Search Results

C4466

Abstract: FG484 CQ256 FG144 D1425 ACTEL SI-SXA-APATQ100-A-KIT SI-SX72-ACQ256SFG484 A54SX72A C4002
Contextual Info: 0HFKDQLFDO 'UDZLQJV IRU WKH $GDSWHU %RDUG S/N Package Device Actel Part Number 1 CQ256 to FG484 For A54SX72A and RT54SX72S devices SI-SX72-ACQ256SFG484 Ironwood Electronics Part Number: CQ256 to FG484 adapter for SX32 And SX72.pdf C4002

CAN bus principle

Abstract: bosch can 2.0B PCA82C250T can controller bosch EASY 3265 bosch
Contextual Info: Implementation of the Basic CAN specification No generated Overload Frames CAN Bus Controller Core Receiving and transmitting of both identifiers CAN specification 2.0B Programmable data rate up to 1 mbps Programmable baud rate prescaler (up to 1/30) The development of increasingly complex microsystems requires the usage of powerful

A54SX08

Abstract: A54SX08A A54SX16 A54SX16A A54SX32 A54SX32A A54SX72A PAR64
Contextual Info: v3.0 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for

54SX32

Abstract: 54SX32A SX FPGAs A54SX32 A54SX32A A54SX72A PAR64 REQ64
Contextual Info: Preliminary v1.0 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • QML Certified Devices • 215 MHz System Performance Military Temperature • 100% Military Temperature Tested (–55°C and +125°C) • 5.3ns Clock-to-Out (Pin-to-Pin) (Military Temperature)

A54SX72

Contextual Info: ^ c te l P r e lim in a r y v1„0 CorePCI Target+DMA Master 33/66MHz P ro d u ct S um m ary Section In te n d e d U s e • High-Performance 33MHz or 66MHz PCI Target+DMA Master Applications Page I/O Signal Descriptions 415 Supported Comm ands 418 Device Utilization

AX2000-CQ256

Contextual Info: Power Matters. Spaceflight FPGAs RTAX -S/SL RTAX-DSP RT-ProASIC 3 RTSX-SU The leader in programmable digital logic integration for spaceflight applications. Taking Designs from Earth to Outer Space Whether you’re designing for low earth orbit, deep space, or anything in between, Microsemi’s high reliability, low

THERMAL Fuse m20 tf 115 c

Abstract: SX v3.1 REQ64 A54SX08 A54SX16 A54SX32 PAR64 313 pin PBGA fq1200 THERMAL Fuse l20 tf 115 c
Contextual Info: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates

22B2 DIODE

Abstract: Theta JC of FBGA A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144 TQ176
Contextual Info: v5.3 SX-A Family FPGAs u e Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops

sx 2082

Contextual Info: v3.0 54SX Family FPGAs Lead ing E dge P er f or m ance Feat ur es • 320 MHz Internal Performance • 66 MHz PCI • 3.7 ns Clock-to-Out Pin-to-Pin • CPLD and FPGA Integration • 0.1 ns Input Set-Up • Single Chip Solution • 0.25 ns Clock Skew • 100% Resource Utilization with 100% Pin Locking

ACTEL FBGA 144

Abstract: A54SX16A
Contextual Info: v2.0  SX-A Automotive Family FPGAs Specifications • 12,000 to 108,000 Available System Gates • Up to 360 User-Programmable I/O Pins • Up to 2,012 Dedicated Flip-Flops • 0.22µ CMOS Process Technology Features u e • Nonvolatile • Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,

tms 980 can bus automotive

Abstract: ProASIC PLUS
Contextual Info: v2.0  SX-A Automotive Family FPGAs Specifications • 12,000 to 108,000 Available System Gates • Up to 360 User-Programmable I/O Pins • Up to 2,012 Dedicated Flip-Flops • 0.22µ CMOS Process Technology Features u e • Nonvolatile • Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,

HiRel a54sx72a unused

Contextual Info: Advanced v1.5 RTSX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

SX-APQ208

Abstract: A54SX16A
Contextual Info: v2.0 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for

SX-APQ208

Abstract: A54SX16A
Contextual Info: v2.0.1 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for

RTSX32SU CQ84

Abstract: Silicon Sculptor II RTSX32SU actel 1020
Contextual Info: v2.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

A54SX08A

Abstract: FBGA-484 LRD12 A54SX16 A54SX16A A54SX32A A54SX72A PAR64 REQ64 54SX72
Contextual Info: Æ ic te ! P r e l i m i n a r y v1 .1 - m SX-AFamily FPGAs L e a d i n g E d g e Pe r f o r m a n e e • Configurable I/O Support for 3.3V5.0VPC3, LVTTL, and TIL • 250 MHz System Performance • Configurable Wfcak Resistor Pullup or Pulldown for

54SX08A

Abstract: 3A03D BC600-3 "network interface cards"
Contextual Info: Application Note Using External SRAM Memory with Actel SX/SX-A FPGAs I n tro du ct i on Today’s system designs are growing in complexity, requiring larger amounts of memory for high-performance buffers and other local data storage. System designs that require both

verilog hdl code for triple modular redundancy

Abstract: Cyclic Redundancy Check simulation Single Event Latchup FPGA 30-80LET ACT 1 FPGA actel
Contextual Info: Real Time Verification/Programming Finishing the Job A c t e l ASICmaster is an automatic place and route tool that runs on SunOS , Solaris®, and HPUX®, as well as on Windows® NT™ . ASICmaster accepts standard ASIC formatted netlists and performs timing-driven place and route. Incremental place and route is supported for

Contextual Info: v2.0 Asynchronous Back-End to PCI Controller Pr od uc t S um m ary G en er al D e sc r i p t i on Intended Use The Asynchronous Back-End Core provides an asynchronous data-transfer channel between the Actel PCI macro running at 33 MHz and a back-end system running at some other

baugh-wooley multiplier verilog

Abstract: 1BG25 LPQ100 9572xv BC356 LPQ240 block diagram baugh-wooley multiplier 4 BIT ALU design with vhdl code using structural XC3000A actel a1240
Contextual Info: LeonardoSpectrum Synthesis and Technology v1999.1 Copyright Copyright 1991-1999 Exemplar Logic, Inc., A Mentor Graphics Company All Rights Reserved Trademarks Exemplar Logic and its Logo are trademarks of Exemplar Logic, Inc. LeonardoSpectrum™, LeonardoInsight™, FlowTabs™, HdlInventor™, SmartScripts™,

register file

Abstract: 54SX-A bgn-tn
Contextual Info: v3.0 Asynchronous Back-End to PCI Controller Pr od uc t S um m ary G en er al D e sc r i p t i on In t e n d e d U s e The Asynchronous Back-End Core provides an asynchronous data-transfer channel between the Actel PCI macro running at 33 MHz and a back-end system running at some other

ACTEL 1020B

Abstract: SIGNAL PATH designer actel 1020
Contextual Info: Application Note Global Clock Networks in Actel Antifuse Devices System performance is one of the most important characteristics of a design. As a result, designers put a lot of effort to improve clock speed. Clock skew is often a limiting factor in attaining maximum performance, forcing

Contextual Info: v2.0 CorePCI Target+DMA 33/66 MHz Pr od u c t S u mm a ry • Compliant with the PCI 2.2 Specification. Intended Use Version • High-Performance PCI Target+DMA Applications This data sheet defines the functionality of Version 5.1 of the CorePCI macro. – 32/64-Bit, 66MHz, 3.3V 66MHz requires the

a54sx72a

Abstract: TQFP-176 footprint A54SX16A A54SX32A-
Contextual Info: Application Note SX to SX-A Design Migration I n tro du ct i on • Configurable Output State During Power Up: All outputs can be programmed to either weak resistor pull up or weak resistor pull down for output tristate. SX-A is fabricated using a 0.22/0.25µ CMOS process. These