PQ208 Search Results

Contextual Info: Product Obsolete/Under Obsolescence R XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table Continued XC4013XLA Pinout Table PAD NAME PQ160 PQ208 PQ240 I/O – – P21 BG256 H1 PAD NAME PQ160 PQ208

Contextual Info: QLUM2208-PQ208C Device Data Sheet • • • • • • Utopia Level 1/Level 2 Master/Master Bridge 1.0 Utopia Level 1/Level 2 Bridge Features • Compliant with ATM-Forum af-phy-0039.000, June 1995 specification • Implements two Utopia L1 or L2 Masters providing a solution to bridge Utopia Slave

Contextual Info: QLUS3316-PQ208C Device Data Sheet • • • • • • Utopia Level 3 Slave Bridges 1.0 Utopia Level 3 L3 Bridge Core Features • Implements two Utopia L3 Slaves providing a solution to bridge Utopia Master devices • Compliant with ATM-Forum af-phy-0136.000 (Utopia L3)

Contextual Info: QLUM3317-PQ208C Device Data Sheet • • • • • • Utopia Level 3 Master/Master Bridge 1.0 Utopia Level 3 L3 Bridge Core Features • Implements two Utopia L3 Masters providing a solution to bridge Utopia Slave devices • Compliant with ATM-Forum af-phy-0136.000 (Utopia L3)

PQ208

Abstract: HQ240 HQFP HQ208 PQ160 HQ160 PQ240 PQ-44
Contextual Info: Package Drawings PQ/HQFP Packages - PQ44, PQ160, PQ208, PQ240, HQ160, HQ208, HQ240 10-30 November 13, 1997 Version 1.2

Contextual Info: QLUS2216-PQ208C Device Data Sheet • • • • • • Utopia Level 2 Slave Bridge 1.0 Utopia Level 2 L2 Bridge Features • Implements two Utopia L2 Slaves providing a solution to bridge Utopia Master devices • Compliant with ATM-Forum af-phy-0039.000, June 1995

Contextual Info: QLUM2216-PQ208C Device Data Sheet • • • • • • Utopia Level 2 Master/Master Bridge 1.0 Utopia Level 2 L2 Bridge Features • Compliant with ATM-Forum af-phy-0039.000, June 1995 specification • Implements two Utopia L2 Masters providing a solution to bridge Utopia Slave devices

CQ256

Abstract: CQ208 4PMX 4pm smd
Contextual Info: te /e • / Speed Grade JTAG I/O 3.3 Volt 5 Volt PCI 5.0 Volt Tolerant at 3.3V VQ100 Std, - 1 , - 2 , - 3 129 8,000 256 512 - — Yes Yes — — Yes PQ208 Std, - 1 , - 2 , - 3 129 8,000 256 512 — — Yes Yes — — Yes TQ144 Std, - 1 , - 2 , - 3 129 8,000

Contextual Info: QLUM2208-PQ208C Device Data Sheet • • • • • • Utopia Level 2 Master/Master Bridge 1.0 Utopia Level 2 L2 Bridge Features • Compliant with ATM-Forum af-phy-0039.000, June 1995 specification • Implements two Utopia L2 Masters providing a solution to bridge Utopia Slave devices

Contextual Info: QLUS3309-PQ208C Device Data Sheet • • • • • • Utopia Level 3 Slave Bridges 1.0 Utopia Level 3 L3 Bridge Core Features • Implements two Utopia L3 Slaves providing a solution to bridge Utopia Master devices • Compliant with ATM-Forum af-phy-0136.000 (Utopia L3)

vq80

Abstract: A40MX02 one time
Contextual Info: Revision 3 40MX and 42MX Automotive FPGA Families Features High Capacity Ease of Integration • Single-Chip Applications ASIC Alternative for Automotive • Up to 100% Resource Utilization and 100% Pin Locking • 3,000 to 54,000 System Gates • Deterministic, User-Controllable Timing

antifuse programming technology

Abstract: 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 42MX24
Contextual Info: v6.0 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y • • • • • • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM

ad 161

Abstract: vhdl code PN code generator ad 152 transistor ad 153 transistor S-108 PF144 PQ208 QL5130 QL5130-33APF144C QL5130-33APQ208C
Contextual Info: QL5130 - QuickPCITM 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM last updated 12/1099 Device Highlights DEVICE HIGHLIGHTS Q8DÃ7ˆ†Ã±Ã""ÃHC“Ã"!Ãiv‡†Ãqh‡hÃhqÃhqq…r†† High Performance PCI Controller • 32-bit / 33 MHz PCI Target

ACTEL FUSION AFS1500

Abstract: FlashPro3 PQ208 QN108 QN180 M1AFS1500 AFS250 rc oscillator M-LVDS
Contextual Info: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

A3PE3000L FG484

Abstract: Actel pdf on radio emitter A3PE3000L FG144 FG256 FG324 FG484 PQ208 TDP 245 Y
Contextual Info: v1.3 ProASIC3L Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • Dramatic Reduction in Dynamic and Static Power Savings • 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power • Low Power Consumption in Flash*Freeze Mode Allows for

CORE8051

Abstract: FlashPro3 AES-128 FG256 PQ208 ac motor variable speed control rc oscillator
Contextual Info: Preliminary v0.4 Actel Fusion Mixed-Signal FPGA for the MicroBlade Advanced Mezzanine Card Solution Features and Benefits • Targeted to Advanced Mezzanine Card AdvancedMC Designs • Designed in Partnership with MicroBlade • 8051-Based Module Management Controller (MMC)

AFS600-FG256

Abstract: zo 103 ma 75 607 A54 ZENER flashpro3 schematic mark AT0 Unipolar PC atx 400 P4 power supply diagram zener Diode B23 PQ208 QN108 QN180
Contextual Info: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

Actel A1225

Abstract: PL84 A1240XL actel a1240 A32140 PQ100C Cadence TQ176 PG176
Contextual Info: ^ c te l - w Integrator Series FPGAs: 1200XL and 3200DX Famüies Features a 4 L. ¡§ Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsvs, and Viewlogic. High C a p a c ity • IEEE Standard 1149.1 JTAG Boundary Scan Testing.

49C466

Contextual Info: 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT IDT49C466 IDT49C466A FEATURES: DESCRIPTION: • 64-bit wide Flow-thruEDC • Separate System and Memory Data Input/Output Buses • — Error Detect Time: 10ns — Error Correct Time: 15ns • Corrects all single bit errors; Detects all double bit errors

Contextual Info: LS125 Data Sheet I-Cube SATC Controller Description Features 33 M Hz 32-bit PCI bus interface, 8 interrapt lines to support up to 8 LS port controllers. 32 or 48 bit Interface with standard asynchronous SRAM to internal port map registers cache up to 128K MAC addresses.

A54 ZENER

Abstract: AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM
Contextual Info: v2.0 Actel Fusion Family of Mixed-Signal FPGAs Features and Benefits In-System Programming ISP and Security High-Performance Reprogrammable Flash Technology Advanced Digital I/O • • • • • Secure ISP with 128-Bit AES via JTAG • FlashLock® to Secure FPGA Contents

74 164 14 PIN DIAGRAM

Abstract: QL5022 QL5022-33APQ208C QL5022-33BPF144C PCI32 PF144 PQ208
Contextual Info: QL5022 QuickPCI Data Sheet •••••• 33 MHz/32-bit PCI Host Capable Master Target with Embedded Programmable Logic Device Highlights Programmable Logic • 387 Logic Cells High Performance PCI Controller • 32-bit / 33 MHz PCI Master/Target with

transistor bl p89

Abstract: bl p74 transistor J955 XC4000 XC4000A XC4000D XC4000E XC4000EX XC4000H p180 g8
Contextual Info: book XC4000E and XC4000X Series Field Programmable Gate Arrays R January 29, 1999 Version 1.5 6* XC4000E and XC4000X Series Features Note: XC4000 Series devices described in this data sheet include the XC4000E family and XC4000X Series. XC4000X Series devices described in this data sheet

Contextual Info: Integrator Series FPGAs - 1200XL and 3200DX Famüies Features Cadence, Escalade, Exemplar, 1ST, M entor Graphics, Synopsys and Viewlogic High C a p a c ity • JTAG1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM