AX125 Search Results

VT6212

Abstract: REF5C486 "USB Controller" mini pci mini pci to pci ricoh packing
Contextual Info: AX10442 PC/104+ 32-bit Card Bus Carrier Module AX12500 PC/104+ to Mini PCI Carrier Module with USB 2.0 Features Features High performance PC/104+ Bus High performance (PC/104+ Bus) 32-bit Card Bus with double deck socket Flexible extension through Mini PCI

8kx1 RAM

Abstract: 8kx1
Contextual Info: Application Note Axcelerator Family Memory Blocks I n tro du ct i on blocks in each device depends on the number of core tiles. For example, in an AX125 device with a single core tile, the number of available memory blocks is 4, while the AX500, with four core tiles, has 16 memory blocks. Note that the

8kx1 RAM

Abstract: AX125 AX2000 AC164
Contextual Info: Application Note AC164 Axcelerator Family Memory Blocks I n tro du ct i on blocks in each device depends on the number of core tiles. For example, in an AX125 device with a single core tile, the number of available memory blocks is 4, while the AX500, with four core tiles, has 16 memory blocks. Note that the

VIA VT6212

Contextual Info: AX12500 PC/104-Plus to MiniPCI Carrier Module with USB 2.0 Features High performance PC/104-Plus Bus Flexible expansion through MiniPCI 4 USB 2.0 PCI104 MiniPCI USB PC/104 Packing List System USB Controller S/W Driver USB Ports Data Bus Mini PCI PCI Interface

CCGA

Abstract: 896-Pin 624 CCGA AD 149 AE9 FBGA 63 AX125 FBGA 896
Contextual Info: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View v2.3 3-1 Axcelerator Family FPGAs 180-Pin CSP 180-Pin CSP AX125 Function Pin Number

729-Pin

Abstract: Axcelerator FPGAs AX125 IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs
Contextual Info: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at

LCD 16PIN

Abstract: 9 pin mini-din connector RS-232 to 8 pin mini-din lvds 20 pin lcd 24 bit lvds lcd interface DF9-41P-1V 24 bit lvds lcd Diskonchip lcd 10 LVDS connector 32 pins LCD
Contextual Info: Ethernet CRT/LCD STB97300 PC/104 DiskOnChip 2 COM AC'97 Audio PC/104+ PC/104+ STX SoM & Baseboards PC/104 F.F. STX Baseboard with Multiple I/O Features Features LCD CRT and full LCD TFT/STN/DSTN 10/100Base-T Ethernet Audio Parallel Port COM Ports RJ-45

10uH inductor CC TECHNOLOGIES

Abstract: APA150 -TQ1001 datasheet AX2000 ISL6528 HSOP-28 thermal Actel APA075 ax rubycon capacitor 106 35K 7 pin str for 24v 3 amp to 220 package APA600
Contextual Info: HIGH PERFORMANCE ANALOG Power Management Application Guide for Actel FPGAs Using Switchers to Power Actel FPGAs FPGAs continue to grow in density and complexity while at the same time, shrinking device geometries have enabled faster system clocks and required lower core voltages. These trends call for more

MAX126

Contextual Info: ADVANCE INFORMATION AI! information in this data sheet is preliminary and subject to change. I ÆÆLJBk W t • Æ W \ÆA o / i? / 2x4-Channel, Sim ultaneous-Sam pling 14-Bit DAS _ Features ♦ Four Simultaneous-Sampltng T/H Amplifiers

verilog code for fir filter using DA

Abstract: A3P1500 vhdl code of 32bit floating point adder digital FIR Filter verilog code digital FIR Filter VHDL code fir vhdl code FIR Filter verilog code vhdl code for floating point adder IQ GENERATOR CODE WITH VHDL RTAX2000
Contextual Info: CoreFIR Finite Impulse Response FIR Filter Generator Product Summary Core Deliverables • Intended Use • – Finite Impulse Response (FIR) Filter for Actel FPGAs • Key Features • – • Self-Checking – Executable Tests Generated Output against Algorithm

avnet

Abstract: ProASIC3 A3P250 A3P250 APA075 AX125
Contextual Info: AvnetCore: Datasheet Version 1.0, July 2006 UTOPIA Level 2 PHY Features: — Supports Actel Axcelerator devicesI/O Peripherals — Compliant with ATM Forum af-phy-0017.000 and af-phy-0039.000 — Supports up to 31 PHYs MC-ACT-UL2PHY Transmit Interface ING_CLK

verilog code for implementation of des

Abstract: vhdl code for DES algorithm RTAX1000S rtax1000 verilog code for des vhdl code for des decryption data encryption standard vhdl wireless encrypt
Contextual Info: Core3DES Product Summary Intended Use • Whenever Data Is Transmitted Across an Accessible Medium wires, wireless, etc. • E-Commerce Transactions, Where Dedicated Encryption/ Decryption Hardware Can Ease the Load on Servers Core Deliverables • Evaluation Version

RTAX2000

Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84
Contextual Info: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

bga 896

Abstract: AX1000
Contextual Info: Product Brief Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • 350+ MHz System Performance 500+ MHZ Internal Performance High-Performance Embedded FIFOs 622Mb/s LVDS Capable I/Os S pe ci fi c at i on s • • • • • Up to 2 Million Equivalent System Gates

Contextual Info: v2.6 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

uart 8250

Abstract: UART using VHDL 8250 uart 8250 uart block diagram uart vhdl verilog code for baud rate generator block diagram UART using VHDL 8250 uart datasheet verilog code for UART baud rate generator 8250
Contextual Info: AvnetCore: Datasheet Version 1.0, July 2006 Universal Asynchronous Rx/Tx Intended Use: — Serial data communications applications — Logic consolidation UART Core IER[�:0 ] RX_CE SIN FFULL FMODE_RX LSR_ACK RBR_ACK RBR[7:0] FWRITE LSR[6:0] UART_RECV CLK

ACTEL CCGA 1152 mechanical

Abstract: AX125 AX2000 CQ208 CQ256 CS180 FG256 PQ208 Trd16 Axcelerator Family FPGAs
Contextual Info: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

ACTEL CCGA 1152 mechanical

Abstract: CS180 antifuse AX125 AX2000 CQ208 CQ256 FG256 PQ208 ACTEL CCGA 624 mechanical
Contextual Info: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

a2f500m3g

Abstract: vhdl code for 8 bit ODD parity generator
Contextual Info: Core16550 v3.1 HandBook Core16550 v3.1 HandBook Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Supported Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

K1259

Abstract: DS1259 MAX1259 MAX1259CPE MAX1259CWE MAX1259EPE MAX1259EWE MAX1259MJE capacitors BF
Contextual Info: JVWVAXJX/X 19-4638; Rev. 1; 4/94 M A X I2 5 9 B a tte r y M a n a g e r Th e M A X 1 2 5 9 b a tte ry m a n a g e r p ro v id e s b a c k u p -b a tte ry s w itc h in g fo r C M O S R AM , m ic ro p ro c e s s o rs , or oth er lo w -p o w e r lo g ic ICs. It a u to m a tic a lly s w itc h e s to the

dunlop s 708

Abstract: PTI 30 040 ga AX125 AX2000 CS180 FG256 FG324 FG484 PQ208 M33 thermal fuse
Contextual Info: Advanced v1.5  Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO"

MAX1004

Abstract: MX7582
Contextual Info: A/D Converters Ultra-High-Speed Conversion d p s 4 Bits Fast Conversion (<100ps) (SAR/Flash A D C s) 8 Bits External T/H — 10 Bits Single Channel see next page for Slow Conversion (>1 Oms) 12 Bits Single Channel - 14 Bits Single Channel 16 Bits Internal T/H

CORE8051

Abstract: vhdl code for i2c Slave 54SX A42MX16 A500K050 A54SX16 A54SX16A APA075 AX125 vhdl code for i2c register
Contextual Info: v1.0 I2C Bus Controller CoreI2C v2.0 Pr od u c t S u mm a ry In te n d e d U s e • I2C bus controller • Supports 100kbps and 400kbps modes Ke y F ea t u re s • Master Transmitter Mode - Serial Data Output through SDA while SCL Outputs the Serial Clock

ACTEL CCGA 1152 mechanical

Abstract: lga 4x4 footprint AX125 AX2000 CQ208 CS180 FG256 PQ208 624-Pin tx 434
Contextual Info: v2.7 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates