8KX1 Search Results

memoire

Abstract: RAM EDAC SEU 350Krad
Contextual Info: 0.6µm CMOS TECHNOLOGY WITH RADIATION TOLERANT FEATURES APPLICATION TO 8Kx16 DUAL PORT RAM and SEA of GATES TECHNOLOGIE CMOS 0.6µm TOLERANTE AUX RADIATIONS APPLICATION A LA MEMOIRE DOUBLE ACCES 8Kx16 ET AUX MERS DE PORTES by Thierry CORBIERE, Valerie LASSERE, Bruno THOMAS, Saïd HACHAD 1

krad

Abstract: 67025E TM1019 RAM SEU
Contextual Info: DPR SCMOS2 Technology Dual Port RAM 8K16 Tolerance to Radiation Abstract This paper proposes a review of the data gathered during radiation testing for the 8Kx16 dual port RAM manufactured using the Radiation Tolerant version of the 0.6µm SCMOS2/2 technology. Both Upset sensitivity

LT 543 IC pin diagram

Abstract: pin diagram of lt 542
Contextual Info: MT56C0818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM |U |C R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4K x 18 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • Operates as two 4K x 18 SRAM s w ith common addresses and data; also configurable as a single

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors :JÖi'Np Jdt) PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Common I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

8kx1 RAM

Abstract: 125 va pt dty 8kx1
Contextual Info: 3.3V 12 8K 8Kx1 6-BIT CACHE-TAG SRAM For 3.3V P r o c e s s o r s FEATURES: H IG H M A T C H o u tp u t is g e n e ra te d w h e n th e s e tw o g ro u p s of d a ta a re th e s a m e fo r a g iven a d d re ss. T h is h ig h -sp e e d M A T C H sig n a l is a v a ila b le as soon a s 10 n s a fte r the a d d re ss

pin diagram of IC 74LS373

Contextual Info: M IC R O N MT56C0816 CACHE DATA SRAM DUAL 4Kx16 SRAM, SINGLE 8Kx16 SRAM CONFIGURABLE CACHE DATA SR A M FEATURES • O perates as two 4K x 16 SRAM s with common ad dresses and data; also configurable as a single 8K x 16 SRAM • Built-in input ad dress latches

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8 K x 16 C onfiguration - 14 Com m on I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • O ptim ized for 256KB cache and 4G B cacheable space

8kx16bit ram

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8 K x 16 C onfiguration - 14 Com m on I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • O ptim ized for 256KB cache and 4G B cacheable space

em78p803

Abstract: em78p EM78801 ICE803 SEG23
Contextual Info: ELAN MICROELECTRONICS CORP. EM78P803, EM78801, EM78805C difference: ICE803 for 805C mode ICE803 for 803 mode EM78P803 for 805c mode EM78P803 for 803 mode EM78801 EM78805C IC type Romless Romless OTP OTP Mask Mask Program ROM 12kx13 16kx13 8kx13 8kx13 8kx13

Contextual Info: M IC R O N * MT56C2818 8 K x 18, DUAL 4 K x 18 CACHE DATA SRAM CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • A u tom atic W RITE cycle com pletion • O p erates a s tw o 4K x 18 SR A M s w ith com m on

Contextual Info: MT56C3818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM M IC R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 18 SRAMs with common addresses and data; also configurable as a single 8K x 18 SRAM

block diagram of 486

Abstract: sram with address counter
Contextual Info: QS88181 Q High-Speed CMOS_ o _ r _ _ _ _ _ _ 8Kx18 Burst Mode SRAM with Address Counter QS88181 « n \/A M rc ADVANCE INFORMATION FEATURES/BENEFITS • • • • 8Kx18with burst mode for secondarycache 1 clock initial access +1 clock/word 40, 33, 25 MHz clock frequency

DSP56116

Abstract: DSP56166 8Kx16 XC56166FE fully differential opamp
Contextual Info: MOTOROLA DSP Division DSP56166 - Rev. E17T XC56166FE E17T Silicon Enhancement Issue date: April 28th 1994 This information constitutes manual errata The following enhancements have been made from the E52N silicon to the E17T silicon: 1- Increased PROM size from 8Kx16 to 12Kx16

SE012

Abstract: 00000000ED SE012 diagram EM- 546
Contextual Info: UM5238 4-Bit Microcontroller with 32 Sec. Voice Synthesizer, LCD Driver and PSG Preliminary Features • ■ ■ ■ ■ m ■ ■ ■ ■ ■ ■ ■ 4-bit parallel processing ALU com patible w ith UM6610 8Kx16 bits program ROM bank switchable 128x 4 bits data RAM

TAG12

Abstract: TAG10_ tag13 8kx16bit cache tag Static RAM
Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

S6H2

Contextual Info: IDT 7MB6042 8KX112 Integrated Device Technology, Inc. WRITABLE CONTROL STORE STATIC RAM MODULE FEATURES: • 8K x 112 high-perform ance W ritable Control Store WCS • Serial Protocol Channel (SPC )-reading, writing and interrogation • High fanout pipeline register

8Kx16

Abstract: TM1019
Contextual Info: Evaluation Report SCMOS2 Radiation Tolerant Technology Dual Port RAM 8Kx16 Tolerance to Radiation by Thierry CORBIERE 1 Work partially funded by French Space Agency [1] Abstract This paper proposes a review of the data gathered during radiation testing for the 8Kx16 dual port

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Com m on I/O TA G Bits - 2 S eparate I/O Status Bits (VLD and D TY) • Optim ized for 256K B cache and 4G B cacheable space

8kx16bit ram

Abstract: 8kx16bit trz a7
Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

CY7C4255V

Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V
Contextual Info: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to

CY7C4255

Abstract: CY7C4265 CY7C42X5
Contextual Info: CY7C4255 CY7C4265 8K/16K x 18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide

2561b

Abstract: CPU 314 IFM 8kx1 RAM cy17 ALI chipset fast page mode dram controller CY2254ASC-2 CY27C010 CY82C691 CY82C693
Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support for standard 72-bit-wide DRAM banks Supports non-symmetrical DRAM banks

Contextual Info: TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584F – APRIL 2009 – REVISED OCTOBER 2011 www.ti.com Piccolo Microcontrollers Check for Samples: TMS320F28030, TMS320F28031, TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035

Contextual Info: HIGH-SPEED 3.3V 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS PRELIMINARY IDT70V7278S/L Features 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture * processor communications; interrupt option Interrupt flags with programmable masking