8KX1 Search Results

memoire

Abstract: RAM EDAC SEU 350Krad
Contextual Info: 0.6µm CMOS TECHNOLOGY WITH RADIATION TOLERANT FEATURES APPLICATION TO 8Kx16 DUAL PORT RAM and SEA of GATES TECHNOLOGIE CMOS 0.6µm TOLERANTE AUX RADIATIONS APPLICATION A LA MEMOIRE DOUBLE ACCES 8Kx16 ET AUX MERS DE PORTES by Thierry CORBIERE, Valerie LASSERE, Bruno THOMAS, Saïd HACHAD 1

krad

Abstract: 67025E TM1019 RAM SEU
Contextual Info: DPR SCMOS2 Technology Dual Port RAM 8K16 Tolerance to Radiation Abstract This paper proposes a review of the data gathered during radiation testing for the 8Kx16 dual port RAM manufactured using the Radiation Tolerant version of the 0.6µm SCMOS2/2 technology. Both Upset sensitivity

LT 543 IC pin diagram

Abstract: pin diagram of lt 542
Contextual Info: MT56C0818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM |U |C R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4K x 18 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • Operates as two 4K x 18 SRAM s w ith common addresses and data; also configurable as a single

Contextual Info: ENERGY METER: Embedded DSP AFE Embedded dspConverters AD73560 AD73560 8/9/01 40 80 2:11 PM AD73360 AD73360 ADSP2185L ADSP2185L 52 52 19 19 16.7 to 26 16.7 to 26 8Kx24 16Kx24 Ed Grokulsky 8Kx16 16Kx16 Rev-4 12/03/00 YES YES YES YES YES YES A A 119 BGA 119 BGA

block diagram of 486

Contextual Info: QS88181 Q High-Speed CMOS 8Kx18 Burst Mode SRAM . « i l a , with Address Counter QS88181 ,I w bdM ,!;Aî TÏ,I OoIN Nf Fo OaR FEATURES/BENEFITS • • • • 8Kx18with burst mode for secondary cache 1 clock initial access + 1 clock/word 40, 33, 25 MHz clock frequency

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors :JÖi'Np Jdt) PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Common I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

8kx1 RAM

Abstract: 125 va pt dty 8kx1
Contextual Info: 3.3V 12 8K 8Kx1 6-BIT CACHE-TAG SRAM For 3.3V P r o c e s s o r s FEATURES: H IG H M A T C H o u tp u t is g e n e ra te d w h e n th e s e tw o g ro u p s of d a ta a re th e s a m e fo r a g iven a d d re ss. T h is h ig h -sp e e d M A T C H sig n a l is a v a ila b le as soon a s 10 n s a fte r the a d d re ss

pin diagram of IC 74LS373

Contextual Info: M IC R O N MT56C0816 CACHE DATA SRAM DUAL 4Kx16 SRAM, SINGLE 8Kx16 SRAM CONFIGURABLE CACHE DATA SR A M FEATURES • O perates as two 4K x 16 SRAM s with common ad dresses and data; also configurable as a single 8K x 16 SRAM • Built-in input ad dress latches

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8 K x 16 C onfiguration - 14 Com m on I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • O ptim ized for 256KB cache and 4G B cacheable space

8kx16bit ram

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8 K x 16 C onfiguration - 14 Com m on I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • O ptim ized for 256KB cache and 4G B cacheable space

em78p803

Abstract: em78p EM78801 ICE803 SEG23
Contextual Info: ELAN MICROELECTRONICS CORP. EM78P803, EM78801, EM78805C difference: ICE803 for 805C mode ICE803 for 803 mode EM78P803 for 805c mode EM78P803 for 803 mode EM78801 EM78805C IC type Romless Romless OTP OTP Mask Mask Program ROM 12kx13 16kx13 8kx13 8kx13 8kx13

Contextual Info: M IC R O N * MT56C2818 8 K x 18, DUAL 4 K x 18 CACHE DATA SRAM CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • A u tom atic W RITE cycle com pletion • O p erates a s tw o 4K x 18 SR A M s w ith com m on

Contextual Info: MT56C3818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM M IC R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 18 SRAMs with common addresses and data; also configurable as a single 8K x 18 SRAM

block diagram of 486

Abstract: sram with address counter
Contextual Info: QS88181 Q High-Speed CMOS_ o _ r _ _ _ _ _ _ 8Kx18 Burst Mode SRAM with Address Counter QS88181 « n \/A M rc ADVANCE INFORMATION FEATURES/BENEFITS • • • • 8Kx18with burst mode for secondarycache 1 clock initial access +1 clock/word 40, 33, 25 MHz clock frequency

SE012

Abstract: 00000000ED SE012 diagram EM- 546
Contextual Info: UM5238 4-Bit Microcontroller with 32 Sec. Voice Synthesizer, LCD Driver and PSG Preliminary Features • ■ ■ ■ ■ m ■ ■ ■ ■ ■ ■ ■ 4-bit parallel processing ALU com patible w ith UM6610 8Kx16 bits program ROM bank switchable 128x 4 bits data RAM

TAG10_

Abstract: tag12 TAG13 8kx16bit
Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

TAG12

Abstract: TAG10_ tag13 8kx16bit cache tag Static RAM
Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

Contextual Info: TM59PA80 8 Bit Microcontroller FEATURES 1. Memory ‧ 212-byte general purpose register include LCD-Buffer RAM ‧ 8Kx14 internal program memory (OTP ROM) 2. Oscillation Sources ‧ Crystal, Ceramic, Ext RC, SUB Clock ‧ CPU clock divider (1/2, 1/8, 1/16, 1/32)

S6H2

Contextual Info: IDT 7MB6042 8KX112 Integrated Device Technology, Inc. WRITABLE CONTROL STORE STATIC RAM MODULE FEATURES: • 8K x 112 high-perform ance W ritable Control Store WCS • Serial Protocol Channel (SPC )-reading, writing and interrogation • High fanout pipeline register

8Kx16

Abstract: TM1019
Contextual Info: Evaluation Report SCMOS2 Radiation Tolerant Technology Dual Port RAM 8Kx16 Tolerance to Radiation by Thierry CORBIERE 1 Work partially funded by French Space Agency [1] Abstract This paper proposes a review of the data gathered during radiation testing for the 8Kx16 dual port

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Com m on I/O TA G Bits - 2 S eparate I/O Status Bits (VLD and D TY) • Optim ized for 256K B cache and 4G B cacheable space

8kx16bit ram

Abstract: 8kx16bit trz a7
Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

Contextual Info: KM 71 8V787 1 2 8 K x 1 8 S y n c h r o n o u s SR A M Document Title 1 2 8Kx1 8-Bi t S y n c h r o n o u s B u r s t S R A M , 3. 3V P o w e r D a t a s h e e t s for 1 0 0 T Q F P Revision History Rev. No. H Istorv Draft Date R e m ar k Rev. 0.0 Initial draft

sram with address counter

Abstract: RISC and CISC COUNTER LOAD
Contextual Info: QS88181 Q High-Speed CMOS_ _ w _ r _ 8Kx18 Burst Mode SRAM with Address Counter Q S88181 a ni/ ADVANCE IN FO R M A TIO N F E A T U R E S /B E N E F IT S • • • • 8Kx18with burst mode for secondary cache 1 clock initial access +1 clock/word 40, 33, 25 MHz clock frequency