8KX18 Search Results

LT 543 IC pin diagram

Abstract: pin diagram of lt 542
Contextual Info: MT56C0818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM |U |C R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4K x 18 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • Operates as two 4K x 18 SRAM s w ith common addresses and data; also configurable as a single

Contextual Info: M IC R O N * MT56C2818 8 K x 18, DUAL 4 K x 18 CACHE DATA SRAM CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • A u tom atic W RITE cycle com pletion • O p erates a s tw o 4K x 18 SR A M s w ith com m on

CY7C4255V

Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V
Contextual Info: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to

CY7C4255

Abstract: CY7C4265 CY7C42X5
Contextual Info: CY7C4255 CY7C4265 8K/16K x 18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide

723653

Abstract: 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’00 IDT FIFO Memory Products Quick Reference Guide

723653

Abstract: BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. Jan’00 IDT FIFO Memory Products Quick Reference Guide

Contextual Info: 2.5 VOLT HIGH-SPEED TeraSync FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,

add round key for aes algorithm

Abstract: detail of half adder ic DIN 5463 2-bit half adder handbook texas instruments IC to design 2 by 2 binary multiplier SE 135 pin configuration verilog code for twiddle factor ROM transistor c789 6A ep3sl1501152
Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.1 July 2010 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

SECDED

Abstract: EP3SE50
Contextual Info: 4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.8 Introduction TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes 640- in ROM mode only or 320-bit memory logic array blocks (MLABs),

CE1X

Abstract: 70V7339 A12L IDT70V7339 IDT70V7339S
Contextual Info: HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V7339S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 512K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 8K x 18 banks

CY7C4255

Abstract: CY7C4265 CY7C42X5 cy7c4255-15ac
Contextual Info: fax id: 5413 1CY 7C42 65 CY7C4255 CY7C4265 8K/16Kx18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide

723653

Abstract: 72V841 72825 72V3622 BI 7284 72V3613 723674 72V211 72V221 72V241
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’99/PC IDT FIFO Memory Products Width

SECDED

Abstract: sram 16k8 EP3SE50
Contextual Info: 4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.1 Introduction TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes 640-bit memory logic array blocks

CY7C4255V

Abstract: CY7C4265V CY7C42X5V
Contextual Info: fax id: 5425 CY7C4255V CY7C4265V PRELIMINARY 8K/16Kx18 Low Voltage Deep Sync FIFOs Features Functional Description • 3.3V operation for low power consumption and easy integration into low voltage systems • High-speed, low-power, first-in first-out FIFO

Contextual Info: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Functional Description F e a tu re s • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out FIFO

70V7339

Abstract: A12L IDT70V7339 IDT70V7339S
Contextual Info: Š HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 512K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 8K x 18 banks – 9 megabits of memory on chip

logic diagram to setup adder and subtractor

Abstract: DIN 5463 add round key for aes algorithm circuit diagram of inverting adder H.264 encoder verilog code for twiddle factor ROM vhdl code for complex multiplication and addition EP3SE50 1517-Pin VHDL codes of 16 point FFT radix-4
Contextual Info: Section I. Device Core This section provides a complete overview of all features relating to the Stratix III device family, which is the most architecturally advanced, high performance, low power FPGA in the market place. This section includes the following chapters:

jd 1803 4 pin

Abstract: FFT CODING BY VERILOG FOR 8 POINT WITH RADIX 2 jd 1803 IC jd 1803 b 107 transistor 3866 s transistor c 6073 circuit diagram verilog code for twiddle factor ROM verilog for Twiddle factor jd 1803 19 B jd 1803 data
Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.1 July 2010 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

Contextual Info: fax id: 5425 ST' CY7C4255V PRELIMINARY _ CY7C4265V 8K/16Kx18 Low Voltage Deep Sync FIFOs Functional Description Features • 3.3V operation for low power consumption and easy integration into low voltage systems • High-speed, low-power, first-in first-out FIFO

BGA 144

Abstract: 208 BGA 72T3665 240-BGA 72T36125
Contextual Info: Selector Guide for TeraSync FIFOs from the leading provider of FIFO solutions • 2.5V core voltage • 225 MHz high-speed operation • Densities up to 9 M-bit • 9, 18, 36, 72-bit configurations • BGA packaging, including JTAG TeraSync the next generation

Sw 2604

Abstract: sem 3040 A 2611 data sheet 1kx8 static ram 54/74 TTL series 16kx8 static ram ttl 6116 sram 6168 sc 64Kx8 dual-port CMOS RAM cmos SRAM 35ns 128k X 8 dip
Contextual Info: Integrated Device Technology, Inc. As of 10/10/95 Page 1 Interactive Product Selector Guide RISC Microprocessors and Embedded Control Products Doc ID Product Product Description Doc ID RISC CPUs 32-bit Speeds Pkgs Temp Volt Cache Other Data Avail Speeds Pkgs

6116 RAM

Abstract: 7217 up down counter ram 6116 256KB static RAM PY 88 74FST3390 7M1002 c 3198 c 3198 transistor dual-port RAM
Contextual Info: Integrated Device Technology, Inc. As of 10/10/95 Page 1 Alpha-Numeric List of Products Doc ID Product Product Description Speeds Pkgs Temp Volt Avail 2760 10474 1KX4 CORNER POWER Bi SRAM, ECL-10K I/O 4ns C 5V Now 2759 10480 16KX1 Bi SRAM, ECL-10K I/O 4ns

Contextual Info: I dt 8K x 36 FIFO MODULE ID T 7 M B 2 0 0 1 S Integrated DeviceTechnology. Inc FEATURES: • Flrst-ln/Flret-Out memory module • Asynchronous and simultaneous read and write • Configurable as 8K x 36 or 16K x 18 unidirectional or 8K x 18 bidirectional FIFO

Contextual Info: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfac­