MT56C Search Results

82385

Abstract: micron memory sram cache micron memory sram intel 82385 74LS373 A12 marking intel sram MT56C0416 1638C 1.2 Micron CMOS Process Family
Contextual Info: ADVANCE M IC R O N MT56C0416 DUAL 4Kx 16/18 SRAM, SINGLE 8Kx 16/18 CACHE DATA STATIC RAMS CO NFIGURABLE CACHE DATA RAM FEATURES PIN A SS IG N M E N T Top View • Operates as two 4K x 16/18 SRAMs with common addresses, common data and separate control signals.

74LS373 PIN CONFIGURATION AND SPECIFICATIONS

Abstract: intel 80386
Contextual Info: MT56C3816 8K x 16, DUAL 4K x 16 CACHE DATA SRAM M IC R O N SINGLE 8Kx 16 SRAM, DUAL 4Kx16 SRAM CACHE DATA SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 16 SRAMs with common addresses and data; also configurable as a single 8K x 16 SRAM

LT 543 IC pin diagram

Abstract: pin diagram of lt 542
Contextual Info: MT56C0818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM |U |C R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4K x 18 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • Operates as two 4K x 18 SRAM s w ith common addresses and data; also configurable as a single

pin diagram of IC 74LS373

Contextual Info: M IC R O N MT56C0816 CACHE DATA SRAM DUAL 4Kx16 SRAM, SINGLE 8Kx16 SRAM CONFIGURABLE CACHE DATA SR A M FEATURES • O perates as two 4K x 16 SRAM s with common ad dresses and data; also configurable as a single 8K x 16 SRAM • Built-in input ad dress latches

Contextual Info: M IC R O N * MT56C2818 8 K x 18, DUAL 4 K x 18 CACHE DATA SRAM CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • A u tom atic W RITE cycle com pletion • O p erates a s tw o 4K x 18 SR A M s w ith com m on

mt90c

Abstract: MT56C0816EJ-25 mt56c0816
Contextual Info: MICRON TECHNOLOGY INC SSE T> WÊ blllSHT 0 0 0 3 ^ 3 7HT B U R N MT56C0816 8K x 16, DUAL 4K x 16 CACHE DATA SRAM V H C Z R O N CACHE DATA SRAM SINGLE 8Kx 16 SRAM, DUAL4KX16 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 16 SRAMs with common

LT 543 IC pin diagram

Abstract: IC SRAM 8K X 8 microprocessor 80386 pin out diagram
Contextual Info: M IC R O N 1 MT56C0818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM T CACHE DATA SRAM SINGLE 8K x18 SRAM, DUAL4 K x 18 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 18 SRAMs with common addresses and data; also configurable as a single 8K x 18 SRAM

Contextual Info: MT56C3818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM M IC R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 18 SRAMs with common addresses and data; also configurable as a single 8K x 18 SRAM

Contextual Info: PRELIMINARY l^ iiczn o N 16K LATCHED SRAM X MT56C16K16B2 16 LATCHED SRAM 16K X 16 SRAM WITH ADDRESS/ DATA INPUT LATCHES, BYTE ENABLES • • • • • • • OPTIONS MARKING • Timing 12ns access 15ns access 20ns access 25ns access -12 -15 -20 -25 • Packages

Contextual Info: PRELIMINARY pilCRON MT56C3818 CACHE DATA C D AM DUAL 4Kx 18 SRAM, SINGLE 8Kx 18 SRAM O CONFIGURABLE CACHE DATA SRAM n M IV I FEATURES PIN ASSIGNMENT Top View • O p era tes a s tw o 4 K x 18 S R A M s w ith co m m on a d d r e sse s a n d d a ta ; a lso co n fig u rab le a s a sin gle

MT56C0816

Abstract: AW 55 IC LT 5251 80386 cache
Contextual Info: M in P n M * ^ MT56C0816 8K x 16, DUAL 4K x 16 CACHE DATA SRAM CACHE DATA SRAM SINGLE 8Kx 16 SRAM, DUAL 4Kx16 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 16 SRAMs with common addresses and data; also configurable as a single 8K x 16 SRAM

Contextual Info: M lfP H M I y MT56C3816 8K x 16, DUAL 4K x 16 CACHE DATA SRAM SINGLE 8 Kx 16 SRAM, DUAL 4K x 16 SRAM CACHE DATA SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 16 SRAMs with common addresses and data; also configurable as a single 8K x 16 SRAM

3B-36

Contextual Info: M RON I I C r-i'-M'v MT56C2818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM S IN G LE 8 K x 1 8 SR A M , D U A L 4K x 18 SRAM CACHE DATA SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Autom atic W RITE cycle completion • Operates as two 4K x 18 SRAM s w ith common

a12w

Abstract: 74LS373 PIN CONFIGURATION AND SPECIFICATIONS
Contextual Info: M IC R O N MT56C0818 DUAL 4 K x 1 8 SRAM, SINGLE 8K x 18 SRAM CACHE DATA SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 18 SRAM s with common ad dresses and data; also configurable as a single 8K x 18 SRAM • Built-in input ad dress latches

Contextual Info: MICRON 16K SYNCHRONOUS SRAM X MT58C1618 18 SYNCHRONOUS SRAM 16K X 18 SRAM WITH CLOCKED, REGISTERED INPUTS FEATURES • • • • • Fast access times: 12,15, 20 and 25ns Fast OE: 5 , 6 , 8 and 10ns Single +5V ±10% power supply Separate, electrically isolated output buffer power

el 803

Contextual Info: A U S T IN SEMICONDUCTOR IN C hQZ D T 0 0 5 1 1 7 OOGOS^O 1R3 « A U S T M T 5 8 C 1 6 1 8 D IE 1 6K X 18 S Y N C H R O N O U S S R A M MICRON T MILITARY SRAM DIE 4 f c - Z .V & 16K x 18 SRAM WITH CLOCKED, REGISTERED INPUTS FEATURES • • • • • •

Contextual Info: |U |I C R O N 128K X M T 58C 1289 9 S Y N C H R O N O U S SRAM 128K x 9 SRAM SYNCHRONOUS SRAM FULLY REGISTERED INPUTS AND OUTPUTS FEATURES PIN ASSIGNMENT Top View T im ing specific to SPARC m icroprocessor Fast cycle times: 12,16.6 and 20ns Fast clock to d ata valid: 6, 8 and 10ns

5550H

Abstract: Bos 6K
Contextual Info: MICRON TECHNOLOGY INC SSE D • b l l l S 4 cî GOGS'ìb'l TS7 URN MT58C1618 DIE 1ÔK X ¡8 SYNCHRONOUS SRAM f f lI C R D M MILITARY SRAM DIE 16K X 18 SRAM WITH CLOCKED, REGISTERED INPUTS FEATURES • • • • DIE OUTLINE Top View Fast access times: 20,25 and 35ns

toshiba 32k*8 sram

Abstract: M5M23C100 M5M5265 seeq DQ2816A M5M23C400 MB832001 HITACHI 64k DRAM TC511000 KM41C464 TC51464
Contextual Info: FUNCTION GUIDE MEMORY ICs 3. CROSS REFERENCE GUIDE 3.1 DRAM Density 64 K X 1 256K X 1 X4 1M X X 4M X X 3.2 Mode Org. 1 4 1 4 Samsung Toshiba Hitachi Fujitsu NEC MSM3764 KM4164 Page Okl F. Page KM41C256 TC51256 Nibble KM41C257 TC51257 HM51256 S. Column KM41C258

DUP1

Contextual Info: FIJCRON TECHNOLOGY INC MICRON SSE T> • blllSMT DD037M3 DT4 ■ URN M T56C 2818 8 K x 18, DUAL 4 K x 18 C A CH E DATA SRAM ■ - ; CACHE DATA -0 4 - q q a i i

82485

Contextual Info: in te i 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Intel486 MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel

Contextual Info: 3ÔE D MICRON TECHNOLOGY INC blllSM'l QGQ3G2Q 1 • MRN r - % - n - ìz aìa r CACHE DATA STATIC RAM DUAL 4Kx 18 SRAM, SINGLE 8Kx 18 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIG N M EN T Top View • Automatic WRITE cycle completion • Operates as two 4K x 18 SRAMs with common

80486 microprocessor pin out diagram

Contextual Info: M IC R O N I l l 1“ 1 M T 56C 3818 8 K x 18, D U A L 4K x 18 C A C H E D A T A S R AM C A C H E DATA single c D U A L 4 K x 18 SRAM d a m O r lM IV I 8K x 18 sram , CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • Operates as two 4K x 18 SRAMs with common

Mil-Std-883 Wire Bond Pull Method 2011

Contextual Info: AUSTIN SEMICONDUCTOR INC büE D • TG02117 0000375 ifl? H A U S T 1 MT58C1616 DIE 16K X 16 SYNCHRONOUS SRAM | u iic = n o N - ■ ' P M W . ' ì - ' S MILITARY SRAM DIE 16Kx 16 SRAM WITH CLOCKED, REGISTERED INPUTS FEATURES •