82385 Search Results

82385

Abstract: intel 80386 block diagram pin configuration of intel 80386 80386 AW12 cache memory OF intel 80386 intel 80386 pin diagram INTEL 80386 25 TA11 chip intel 82385
Contextual Info: VITEUC V63C330 HIGH PERFORMANCE, LOW POWER 8K x 16 B IT CACHE CMOS STATIC RAM Features Description • Designed for 32KB, 64KB and 128KB Cache Implementation ■ Directly interfaces with 82385 Cache Controller High speed • Designed for 80386 Systems at 33/25/20

386SX

Abstract: 82385SX t23b 82358 82385 t44a 387SX SA9C a82385 intel 386 SX LP
Contextual Info: in te i 82385SX HIGH PERFORMANCE CACHE CONTROLLER Im proves 386 SX System Perform ance — Reduces A verage CPU W ait States to Nearly Zero — Zero W ait State Read Hit — Zero W ait State Posted Mem ory W rites — Allows O ther Masters to Access the

Contextual Info: UNITE» MICROELECTRONICS UM82C388 3QE D • ^355655 DOD01 fab 1 5^-33 ^ \ INTEL Cache Interface Features ■ Supports 16 MHz, 20 MHz and 25 MHz Intel 80386 Supports 2 5 6 K and 1M DRAM S ■ Supports 25 MHz 80386 with 82385 cache controller 1.2/it CMOS technology

intel 80386 pin diagram

Contextual Info: ¡r VITELIC V63C329 HIGH PERFORMANCE, LOW POWER 8K x 16 BIT CACHE CMOS STATIC RAM f Features p r e l im in a r y Description • Designed for 64KB and 128KB Cache Implemen­ tation ■ Directly interfaces with 82385 Cache Controller ■ High speed • Designed for 80386 Systems at 33/25/20

82C307

Abstract: 82385 80386 cache 79R3000 UM61166 UM61166-25 UM61166L 82c307 cache controller 80386 intel cache controller
Contextual Info: UNICORN MICROELECTRONICS E4E D =1270700 □□□115b 5 r - w Ü M - z z - i o . U M 61166 Series O 4KX16 CMOS CACHE RAM P R E L IM IN A R Y Features Common I/O using three-state output Direct interface with Intel cache controller 82385 or IDT 79R3000 RISC CPU or C & T cache controller

A82385

Contextual Info: 82385 HIGH PERFORMANCE 32-BIT CACHE CONTROLLER • Improves 386 DX System Performance — Reduces Average CPU Wait States to Nearly Zero — Zero Wait State Read Hit — Zero Wait State Posted Memory Writes — Allows Other Masters to Access the System Bus More Readily

V63C328

Abstract: pin configuration of intel 80386 82385 cache memory OF intel 80386 intel 82385
Contextual Info: IS" T VITELIC V63C328 HIGH PERFORMANCE, LOW POWER 8K x 16 BIT CACHE CMOS STATIC RAM Features Description • High speed • Designed for 80386 Systems up to 33/25/20 MHz • Directly interfaces with 82385 Cache Controller • Maximum access time of 30/40/45 ns

intel 80386 pin diagram

Abstract: 19I20
Contextual Info: MT VITELIC “ V63C330 HIGH PERFORMANCE, LOW POWER 8K x 16 BIT CACHE CMOS STATIC RAM Features Description • Designed for 32KB, 64KB and 128KB Cache Implementation ■ Directly interfaces with 82385 Cache Controller High speed • Designed for 80386 Systems at 33/25/20

82385

Abstract: a82385 intel 82385 82380 INTEGRATED SYSTEM PERIPHERAL 386DX T44A 82380 386DXsystem INTEL 386DX PQFP dimension intel
Contextual Info: in tei 82385 HIGH PERFORMANCE 32-BIT CACHE CONTROLLER Im proves 386 DX System Perform ance — Reduces A verage CPU W ait States to Nearly Zero — Zero W ait State Read Hit — Zero W ait State Posted M em ory Writes — Allows O ther Masters to Access the

Intel 82311

Abstract: 386 MOTHERBOARD
Contextual Info: irrtJ. 82308 Micro Channel BUS CONTROLLER • Micro Channel Compatible Bus Control ■ Supports 8-, 16- or 32-Bit Data Transfers on the Micro Channel ■ Optional Hardware! Enforced I/O Recovery Mechanism ■ Cache Controller 82385 Interface to Maximize Performance for 80386 Based

t44a

Abstract: 82358 29022 A 2232 intel localbus 386 386TM A82385 SES N 2405 386sx
Contextual Info: 82385SX HIGH P E R F O R M A N C E C A C H E C O N T R O L L E R Im proves 386 sx System Perform ance — Reduces Average CPU W ait States to Nearly Zero — Zero W ait State Read Hit — Zero W ait State Posted M em ory W rites — A llow s O ther M asters to Access the

SCAD002

Contextual Info: SN74ACT2140A 2-WAY 4K x 18/8K x 18 CACHE DATA RAM D3291, NO VEM BER 1 989-R E V IS E D JUNE 1990 FN PACKAGE Interfaces Directly with the Intel 82385 Cache Controller TOP VIEW 2 Access T im e . . . 25 ns Max CM CO Tf LO <0 O O LU J N CO o 0 ) t- T- r- < AO

Contextual Info: SN74ACT2140A 2-WAY 4K x 18/8K x 18 CACHE DATA RAM D3291, NOVEMBER 1989-REVISED JUNE 1990 • Interfaces Directly with the Intel 82385 Cache Controller • Access Time . . . 25 ns Max FN PA C K A G E TOP V IE W z • • • I Fast Access Time Supports 33-MHz Intel

transistor marking A9

Abstract: 82385 D016 "256K x 16" SRAM PLCC
Contextual Info: ADVANCE I^ IIC R O N M T5C 6416 SRAM 4K 16 SRAM X LATCHED CACHE DATA RAM FEATURES PIN ASSIGNMENT Top View • On-chip address latch. • Compatible with the Intel 82385 cache memory controller. • Fast access times: 25ns, 35ns and 45ns. • Upper and lower byte selects.

intel 82385

Abstract: 82386 20D11 21G22
Contextual Info: SN74ACT2140A 2-WAY 4K x 18/8K x 18 CACHE DATA RAM D3291, N O VEM BER 1989-R E V IS E D JUN E 1990 FN P ACKA G E Interfaces Directly with the Intel 82385 Cache Controller TOP VIE W T - C M C O T j-in tO I II II 6 II 5 AO ] 8 7 GND ] 9 Configurable for 2-Way or Direct Mapped

80486 microprocessor features

Abstract: 82C482 A38202 V63C430 82c31 pin out of 80386 microprocessor
Contextual Info: i f VITELIC V63C430 2 x 8 K x 16 BIT/16K x 16 BIT CACHE CMOS STATIC RAM ‘ Features PRELIMINARY Description Designed for 64KB, 128KB, and 256KB implementation Direct interface to 82385, A38202, C395e, 82C482 and 82C312 Cache Controllers High Speed • Designed for 80386 and 80486 systems up to

82385

Abstract: TAG 9223 80386 80386 microprocessor pin out diagram c3851 CA9H cache controller C385 80386 specification update SA31-SA2
Contextual Info: m r 30 isst í MDS-C385Ì 32kB 32-BIT CACHE CONTROLLER MATRA DESIGN SEMICONDUCTOR nmm&wry/ July 1990 FEATURES Compatible with Intel 82385 32-bit Write-thru scheme for updating main cache controller memory, including posted write Highly integrated and optimized for

cache memory OF intel 80386

Abstract: intel 82385 intel 80386 pin diagram 82385 80386
Contextual Info: M OSEL APPLICATION NOTE AN-1 Using the MOSEL MS82C308 Cache Data RAM with the Intel 82385 Cache Controller High speed 80386 systems place severe demands on memory designers to develop economical methods to maintain processor throughput without incurring enormous costs. One proven, effective

256K x 8 SRAM dip

Contextual Info: ADVANCE MT5C6416 M IC R O N SRAM 4K 16 SRAM X LATCHED CACHE DATA RAM FEATURES PIN ASSIGNMENT Top View • On-chip address latch. • Compatible with the Intel 82385 cache memory controller. • Fast access times: 25ns, 35ns and 45ns. • Upper and lower byte selects.

TC55188

Abstract: TC55188T-25 TC55188T-20 TC55188T
Contextual Info: •»ilK 2 - W A Y 4,096 W ORDS x 18 BITS/8,192 WORDS x 18 BITS CMOS STATIC CACHE DATA RAM DESCRIPTION The TC55188T is a 147,456bits high-speed static RAM which can be user-configured either a s 2-way 4,096 words by 18 bits or as 8,192 words by 18 bits. It is provided with a byte control, on-chip

um61168

Contextual Info: L I8 V 1 C U M 6 1 1 6 8 Series 2 x 4K x 16 CMOS CACHE RAM P R ELIM IN AR Y Features • S ingle + 5 V p o w e r su pp ly ■ ■ Access tim e s: 2 5 /3 5 /4 5 ns m ax. ■ ■ S u p p o rts h ig h speed 8 0 3 8 6 (3 3 /2 5 /2 0 M H z) w it h fa st ■ C u rre n t:

intel 82310

Abstract: 82310 intel 80387sx intel 80386 motherboard,
Contextual Info: in te T 82310 Micro Channel COMPATIBLE PERIPHERAL CHIP SET • Highly Integrated VLSI Components to Implement Micro Channel Compatible Motherboard ■ Single Architectural Solution for 80386 16 MHz, 20 MHz and 25 MHz systems, and 80386SX 16 MHz Systems

intel 386 motherboard diagram

Abstract: 386SX chipset intel 82395sx 82395sx Intel 386 DX 82395dx Intel CPU 386
Contextual Info: SbE D in te ! • 4Ö2L17S DllS3b2 4T4 ■ I T L 1 INTEL CORP UP/PRPHLS 82311 ' •5 2 -3 > 3 -1 3 HIGH INTEGRATION Micro Channel COMPATIBLE PERIPHERAL CHIP SET Flexible Memory Architecture Support — Up to 4 Banks of Interleaved Page Memory — 256K, 1M, 4M DRAM Support

82385

Abstract: micron memory sram cache micron memory sram intel 82385 74LS373 A12 marking intel sram MT56C0416 1638C 1.2 Micron CMOS Process Family
Contextual Info: ADVANCE M IC R O N MT56C0416 DUAL 4Kx 16/18 SRAM, SINGLE 8Kx 16/18 CACHE DATA STATIC RAMS CO NFIGURABLE CACHE DATA RAM FEATURES PIN A SS IG N M E N T Top View • Operates as two 4K x 16/18 SRAMs with common addresses, common data and separate control signals.