IDT71V218 Search Results

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors :JÖi'Np Jdt) PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Common I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8 K x 16 C onfiguration - 14 Com m on I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • O ptim ized for 256KB cache and 4G B cacheable space

8kx16bit ram

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8 K x 16 C onfiguration - 14 Com m on I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • O ptim ized for 256KB cache and 4G B cacheable space

TAG10_

Abstract: tag12 TAG13 8kx16bit
Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

TAG12

Abstract: TAG10_ tag13 8kx16bit cache tag Static RAM
Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Com m on I/O TA G Bits - 2 S eparate I/O Status Bits (VLD and D TY) • Optim ized for 256K B cache and 4G B cacheable space

8kx16bit ram

Abstract: 8kx16bit trz a7
Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

8kx1 RAM

Abstract: 125 va pt dty 8kx1
Contextual Info: 3.3V 12 8K 8Kx1 6-BIT CACHE-TAG SRAM For 3.3V P r o c e s s o r s FEATURES: H IG H M A T C H o u tp u t is g e n e ra te d w h e n th e s e tw o g ro u p s of d a ta a re th e s a m e fo r a g iven a d d re ss. T h is h ig h -sp e e d M A T C H sig n a l is a v a ila b le as soon a s 10 n s a fte r the a d d re ss