CY7C191 Search Results

7C192-12

Abstract: 7C192-15 7C192-20 A10C CY7C191 CY7C192 CY7C192-25PC
Contextual Info: MbE D CYPRESS SEMICON DUC TOR B 250^fc,b2 OOQfc.1,42 3 E 3 C Y P CY7C191 CY7C192 CYPRESS SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C19X • CMOS for optimum speed/power • H ighspeed — tM = 25 ns • Low active power

7C192-12

Abstract: 7C192-15 A10C CY7C191 CY7C192 CY7C192-25PC
Contextual Info: CY7C191 CY7C192 ir CYPRESS 64K x 4 Static RAM with Separate I/O Features Functional Description • High speed T he CY7C191 and CY7C192 are high­ perform ance CM OS static RAM s orga­ nized as 65,536 x 4 bits with separate I/O. Easy m em ory expansion isprovided by ac­

c1918

Abstract: C1915 CY7C192-25PC 7C192-12 7C192-15 C191 CY7C191 CY7C192 C1914
Contextual Info: 1CY 7C19 2 CY7C191 CY7C192 64K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enable CE and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 75% when deselected.

CY7C1316BV18

Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
Contextual Info: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

CY7C1311CV18

Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
Contextual Info: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■

CY7C1310BV18

Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18
Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR -II SRAM 2 Word Burst Architecture Features Functional Description Separate Independent read and write data ports ❐ Supports concurrent transactions • 250 MHz clock for high bandwidth ■ 2 Word Burst on all accesses

CY7C1311BV18

Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth

Contextual Info: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310KV18 – 2 M x 8 ■ 333 MHz clock for high bandwidth

Contextual Info: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth

Contextual Info: CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • QDR-II operates with 1.5 cycle read latency when the DLL is enabled

Contextual Info: CY7C1317BV18 CY7C1319BV18 CY7C1321BV18 PRELIMINARY 18-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM

Contextual Info: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C191 CY7C192 " ^ cÌ press SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C191 • CMOS for optimum speed/power • High speed — ‘ a a = 2 5 ns • Low active power — 880 raW • Low standby power 65,536 x 4 Static R/W RAM

Contextual Info: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9

Contextual Info: CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth

Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions

93191

Abstract: sumitomo 6300h mold compound CY7C191 CY7C192 CY7C194 CY7C195 CY7C196 CY7C197 CY7C198 CY7C199
Contextual Info: PAGE 1 CYPRESS SEMICONDUCTOR Qualification Report July, 1994, QTP#93192/93191, Version 2.4 256K SRAM, RAM 2.1 SHRINK MARKETING PART NUMBER DEVICE DESCRIPTION CY7C191 64K x 4 Separate IO with transparent write CY7C192 64K x 4 Separate IO without transparent write

CY7C1311BV18

Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth

Contextual Info: CY7C191 CY7C192 PRELIMINARY CYPRESS SEMICONDUCTOR Features Functional Description • High speed — 12 ns • Transparent write 7C191 • CMOS for optimum speed/power • Low active power — 880 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs

Contextual Info: CY7C191 CY7C192 b m - . C Y PR ESS r SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C191 • CMOS for optimum speed/power • Highspeed — tAA = 25 ns • Low active power — 880 mW • Low standby power

Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth

CY7C1316JV18

Abstract: CY7C1318JV18 CY7C1320JV18 CY7C1916JV18
Contextual Info: CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

7C192-12

Abstract: 7C192-15 A10C CY7C191 CY7C192 CY7C192-25PC
Contextual Info: CY7C191 CY7C192 if CYPRESS 64K x 4 Static RAM with Separate I/O Features Functional Description • High speed — 12 ns • Transparent write CY7C191 • CMOS for optimum speed/power • Low active power T he CY7C191 and CY7C192 are highperform ance CM OS static RAM s orga­