CY7C191 Search Results

7C192-12

Abstract: 7C192-15 7C192-20 A10C CY7C191 CY7C192 CY7C192-25PC
Contextual Info: MbE D CYPRESS SEMICON DUC TOR B 250^fc,b2 OOQfc.1,42 3 E 3 C Y P CY7C191 CY7C192 CYPRESS SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C19X • CMOS for optimum speed/power • H ighspeed — tM = 25 ns • Low active power

7C192-12

Abstract: 7C192-15 A10C CY7C191 CY7C192 CY7C192-25PC
Contextual Info: CY7C191 CY7C192 ir CYPRESS 64K x 4 Static RAM with Separate I/O Features Functional Description • High speed T he CY7C191 and CY7C192 are high­ perform ance CM OS static RAM s orga­ nized as 65,536 x 4 bits with separate I/O. Easy m em ory expansion isprovided by ac­

c1918

Abstract: C1915 CY7C192-25PC 7C192-12 7C192-15 C191 CY7C191 CY7C192 C1914
Contextual Info: 1CY 7C19 2 CY7C191 CY7C192 64K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enable CE and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 75% when deselected.

CY7C1316BV18

Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
Contextual Info: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

CY7C1311BV18

Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth

Contextual Info: CY7C191 CY7C192 PRELIMINARY CYPRESS SEMICONDUCTOR Features Functional Description • High speed — 12 ns • Transparent write 7C191 • CMOS for optimum speed/power • Low active power — 880 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs

Contextual Info: CY7C191 CY7C192 b m - . C Y PR ESS r SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C191 • CMOS for optimum speed/power • Highspeed — tAA = 25 ns • Low active power — 880 mW • Low standby power

7C192-12

Abstract: 7C192-15 7C192-20 CY7C191 CY7C192
Contextual Info: bSE SEMICONDUCTOR » SSfl'ibhE OOIOGIE 243 M C Y P CY7C191 CY7C192 PRELIMINARY r^ y p p rc q = SEMICONDUCTOR 64K x 4 Static RAM with Separate I/O Features Functional Description • H ighspeed — 1 2 ns • T ransparent write 7C191 • CMOS for optim um speed/power

CY7C1316CV18

Abstract: CY7C1318CV18 CY7C1320CV18 CY7C1916CV18
Contextual Info: CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

CY7C1318KV18

Abstract: CY7C1318KV18-250 CY7C1320KV18
Contextual Info: CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1316KV18 – 2 M × 8

Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth

Contextual Info: L7 C 191/192 64K x 4 Static RAM DESCRIPTION FEATURES □ 64K x 4 Static RAM with Separate I/O , Transparent Write L7C191 , or High Impedance Write (L7C192) □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 15 ns maximum □ Low Power Operation

Contextual Info: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18

CY62256LL-PC

Abstract: VIC068A-GC VIC64-NC VIC64-UMB PALCE22V10-JI PALC16L8Q PLD VME A113 CY7B923 JESD22-A113
Contextual Info: Cypress Semiconductor Product Reliability 1997 Published June, 1997 CYPRESS SEMICONDUCTOR PRODUCT RELIABILITY TABLE OF CONTENTS 1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM. 1 2.0 ELECTRICAL AVERAGE OUTGOING QUALITY. 2

9235P

Abstract: 9135p
Contextual Info: C Y 7 C 1 9 1 p yp: v « *1 X X C Y 7 C 1 9 2 - 64K x 4 Static RAM with Separate I/O Easy m em ory expansion is provided by active LO W chip e n ­ able UE and th re e -sta te drivers. T hey have an a u to m a tic po w e r-d ow n fea tu re, reducing th e pow er con sum p tion by 75%

Contextual Info: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Configurations Features Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18

EPM5128LC

Abstract: IDT CYPRESS CROSS REFERENCE clocks epm5064lc-1 EPM5128LC-1 EPM5064LC EPM5128LC-2 EPM5128GI EPM5128JC-1 8464c 5962-8871309
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2148-35C CY21L48-35C CY7C168A-35C CY7C168A-25C 5962-8871309XX 5962-89839112X CY2148-35C CY7C148-35C CY7C168A-45M CY7C168A-35M+ 5962-8871310RX 5962-8983913RX CY2148-35M CY7C148-35M CY7C169A-35C

CY7C1320KV18

Contextual Info: CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1318KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth

Contextual Info: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth

Sony CXA1191M

Abstract: philips ecg master replacement guide FZK101 YD 803 SGS FZK 101 Siemens CMC 707 am radio receiver philips ecg semiconductors master replacement guide CXA1191M ym2612 ecg semiconductors master replacement guide
Contextual Info: Untitled HAM RADIO FILE - Various pinouts saved from the Chipdir 2010 http://www.chipdir.org/ 0512d -0512d +-\/-+ 1 -|5V in gnd in|- 24 2 -|5V in gnd in|- 23 3 -|5V in gnd in|- 22

CY7C1318KV18-250BZXC

Abstract: CY7C1320KV18
Contextual Info: CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1318KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth

AN5062

Contextual Info: CY7C1318BV18, CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces

Contextual Info: CY7C1312CV18 CY7C1314CV18 18-Mbit QDR II SRAM 2-Word Burst Architecture 18-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1312CV18 – 1M x 18