CY7C1910BV18 Search Results

CY7C1910BV18 Datasheets (5)

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Cypress Semiconductor

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY7C1910BV18		Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF	264.85KB	23
CY7C1910BV18-167BZC		Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF	264.87KB	23
CY7C1910BV18-167BZXC		Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF	264.85KB	23
CY7C1910BV18-200BZC		Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF	264.87KB	23
CY7C1910BV18-250BZC		Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF	264.87KB	23

CY7C1910BV18 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR -II SRAM 2 Word Burst Architecture Features Functional Description Separate Independent read and write data ports ❐ Supports concurrent transactions • 250 MHz clock for high bandwidth ■ 2 Word Burst on all accesses	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +118-mbit	PDF
Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +218-mbit 250-mhz	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +218-mbit 250-mhz	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 static SRAM single port Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • Core VDD = 1.8V ±0.1V ; I/O VDDQ = 1.4V to VDD The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +218-mbit static sram single port	PDF
Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +218-mbit 250-mhz	PDF
Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +218-mbit 250-mhz	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 CY7C1314BV18-167BZXI Contextual Info: CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 18-Mbit QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +218-mbit cy7c1314bv18-167bzxi	PDF
CY7C1312BV18 Abstract: CY7C1314BV18 CY7C1312 Contextual Info: CY7C1312BV18 CY7C1314BV18 18 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses	Original	cy7c1312bv18 cy7c1314bv18 cy7c1312	PDF
CY7C1312BV18-167BZC Contextual Info: CY7C1312BV18 CY7C1314BV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth	Original	cy7c1312bv18 cy7c1314bv18 18-mbit cy7c1312bv18-167bzc	PDF
CY7C1338-100AXC Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC Contextual Info: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12	Original	cy7c1019bv33-15vc gs71108aj-12 cy7c1019bv33-15vxc gs71108agj-12 +16cy7c1019bv33-15zc gs71108atp-12 cy7c1019bv33-15zxc gs71108agp-12 cy7c1019cv33-10vc gs71108aj-10 cy7c1338-100axc gvt7164d32q-6 cy7c1049bv33-12vxc cy7c1363c-133ac cy7c1021dv33-12zxc cy7c1460av25-200axc cy7c1338g-100ac cy7c1041v33-12zxc cy7c1460v33-200axc cy7c1021dv33-10zxc	PDF
Contextual Info: CY7C1312BV18 CY7C1314BV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth	Original	cy7c1312bv18 cy7c1314bv18 18-mbit	PDF
Contextual Info: CY7C1310BV18 CY7C1312BV18 CY7C1314BV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth	Original	cy7c1310bv18 cy7c1312bv18 cy7c1314bv18 18-mbit +4300-mhz cy7c1910bv18 bb165e bb165d	PDF