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CY7C1312 Datasheets (63)

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Cypress Semiconductor

Part	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY7C131-25JC	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF	310.89KB	16
CY7C131-25JC	Cypress Semiconductor	1024 x 8 Dual-Port Static RAM	Scan	PDF	911.34KB	13
CY7C131-25JC	Cypress Semiconductor	Multiple Array MatriX High-Density EPLDs	Scan	PDF	920.78KB	12
CY7C131-25JC	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Scan	PDF	415.46KB	13
CY7C131-25JI	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF	310.89KB	16
CY7C131-25JI	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Scan	PDF	415.46KB	13
CY7C131-25JXC	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF	376.17KB	19
CY7C131-25JXC	Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 8KBIT 25NS 52PLCC	Original	PDF		22
CY7C131-25JXCT	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF	376.17KB	19
CY7C131-25JXCT	Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 8KBIT 25NS 52PLCC	Original	PDF		22
CY7C131-25LC	Cypress Semiconductor	1024 x 8 Dual-Port Static RAM	Scan	PDF	911.34KB	13
CY7C131-25LC	Cypress Semiconductor	Multiple Array MatriX High-Density EPLDs	Scan	PDF	920.78KB	12
CY7C131-25NC	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF	310.89KB	16
CY7C131-25NC	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF	376.17KB	19

CY7C131-25NC	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Scan	PDF	415.46KB	13
CY7C131-25NI	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF	310.89KB	16
CY7C131-25NI	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Scan	PDF	415.46KB	13
CY7C131-25NXC	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF	376.17KB	19
CY7C131-25NXC	Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 8KBIT 25NS 52QFP	Original	PDF		22
CY7C131-25NXCT	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF	376.17KB	19

CY7C1312 Price and Stock

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Infineon Technologies AG CY7C1312KV18-250BZXCT IC: SRAM memory; 18MbSRAM; 1Mx18bit; FBGA165; parallel; 0÷70°C
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
TME	CY7C1312KV18-250BZXCT				1,000	1 - 10 - 100 - 1000 $36.98 10000 $36.98	Get Quote
Cypress Semiconductor CY7C1312BV18-167BZI SRAM Chip Sync Dual 1.8V 18M-bit 1M x 18 0.5ns 165-Pin FBGA Tray
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical ()	CY7C1312BV18-167BZI		875		25	1 - 10 - 100 $42.63 1000 $38.14 10000 $35.89	Buy Now
	CY7C1312BV18-167BZI		69		25	1 - 10 - 100 $42.63 1000 $38.14 10000 $35.89	Buy Now
	CY7C1312BV18-167BZI		38		25	1 - 10 - 100 $42.63 1000 $38.14 10000 $35.89	Buy Now
Cypress Semiconductor CY7C1312CV18-250BZC SRAM Chip Sync Dual 1.8V 18M-bit 1M x 18 0.45ns 165-Pin FBGA Tray
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical ()	CY7C1312CV18-250BZC		603		25	1 - 10 - 100 $37.74 1000 $33.76 10000 $31.77	Buy Now
	CY7C1312CV18-250BZC		369		25	1 - 10 - 100 $37.74 1000 $33.76 10000 $31.77	Buy Now
Cypress Semiconductor CY7C1312CV18-167BZC CY7C1312CV18-167BZC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical ()	CY7C1312CV18-167BZC		526		25	1 - 10 - 100 $34.49 1000 $30.85 10000 $29.04	Buy Now
	CY7C1312CV18-167BZC		109		25	1 - 10 - 100 $34.49 1000 $30.85 10000 $29.04	Buy Now
Cypress Semiconductor CY7C1312KV18-333BZC SRAM Chip Sync Dual 1.8V 18M-bit 1M x 18 0.45ns 165-Pin FBGA Tray
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical ()	CY7C1312KV18-333BZC		257		25	1 - 10 - 100 $36.50 1000 $32.66 10000 $30.74	Buy Now
	CY7C1312KV18-333BZC		101		25	1 - 10 - 100 $36.50 1000 $32.66 10000 $30.74	Buy Now
	CY7C1312KV18-333BZC		100		25	1 - 10 - 100 $36.50 1000 $32.66 10000 $30.74	Buy Now

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CY7C1312 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18	Original	18-mbit cy7c1312kv18 cy7c1314kv18	PDF
CY7C1310V18 Abstract: CY7C1312V18 CY7C1314V18 Contextual Info: 310V18 CY7C1310V18 CY7C1312V18 CY7C1314V18 ADVANCE INFORMATION 18-Mb 2-Word Burst SRAM with QDR -II Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250 MHz Clock for High Bandwidth	Original	310v18 cy7c1310v18 cy7c1312v18 cy7c1314v18 +218-mb cy7c1310v18/cy7c1312v18/cy7c1314v18	PDF
CY7C1310AV18 Abstract: CY7C1312AV18 CY7C1314AV18 Contextual Info: CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses	Original	cy7c1310av18 cy7c1312av18 cy7c1314av18 18-mb +3167-mhz 167mhz cy7c1310av18/cy7c1312av18/cy7c1314av18	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR -II SRAM 2 Word Burst Architecture Features Functional Description Separate Independent read and write data ports ❐ Supports concurrent transactions • 250 MHz clock for high bandwidth ■ 2 Word Burst on all accesses	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +118-mbit	PDF
Contextual Info: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310KV18 – 2 M x 8 ■ 333 MHz clock for high bandwidth	Original	18-mbit cy7c1310kv18 cy7c1910kv18 cy7c1312kv18 +1cy7c1314kv18	PDF
Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +218-mbit 250-mhz	PDF
Contextual Info: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions	Original	cy7c1310kv18 cy7c1910kv18 cy7c1312kv18 cy7c1314kv18 +118-mbit	PDF
Contextual Info: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9	Original	cy7c1310jv18 cy7c1910jv18 cy7c1312jv18 cy7c1314jv18	PDF
Contextual Info: CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	cy7c1310cv18 cy7c1910cv18 cy7c1312cv18 cy7c1314cv18 +218-mbit 250-mhz	PDF
CY7C1312BV18 Abstract: CY7C1314BV18 CY7C1312 Contextual Info: CY7C1312BV18 CY7C1314BV18 18 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses	Original	cy7c1312bv18 cy7c1314bv18 cy7c1312	PDF
Contextual Info: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Configurations Features Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18	Original	cy7c1312kv18 cy7c1314kv18 18-mbit	PDF
Contextual Info: CY7C1310V18 CY7C1312V18 CY7C1314V18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses	Original	cy7c1310v18 cy7c1312v18 cy7c1314v18 18-mb +2167-mhz 167mhz	PDF
CY7C1312BV18-167BZC Contextual Info: CY7C1312BV18 CY7C1314BV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth	Original	cy7c1312bv18 cy7c1314bv18 18-mbit cy7c1312bv18-167bzc	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +218-mbit 250-mhz	PDF

CY7C1310V18 Abstract: CY7C1312V18 CY7C1314V18 Contextual Info: CY7C1310V18 CY7C1312V18 CY7C1314V18 PRELIMINARY 18-Mb QDR -II SRAM Two-word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth • Two-word Burst on all accesses	Original	cy7c1310v18 cy7c1312v18 cy7c1314v18 18-mb +3167-mhz 167mhz cy7c1310v18/cy7c1312v18/cy7c1314v18	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 static SRAM single port Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • Core VDD = 1.8V ±0.1V ; I/O VDDQ = 1.4V to VDD The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +218-mbit static sram single port	PDF
Contextual Info: CY7C13101KV18, CY7C13251KV18 CY7C13121KV18, CY7C13141KV18 18-Mbit QDR II SRAM 2-Word Burst Architecture 18-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions	Original	18-mbit cy7c13101kv18 cy7c13251kv18 cy7c13121kv18 +1cy7c13141kv18	PDF
Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	cy7c1310bv18 cy7c1910bv18 cy7c1312bv18 cy7c1314bv18 +218-mbit 250-mhz	PDF
Contextual Info: CY7C13101KV18, CY7C13251KV18 CY7C13121KV18, CY7C13141KV18 18-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C13101KV18 – 2M x 8 ■ 333 MHz clock for high bandwidth	Original	18-mbit cy7c13101kv18 cy7c13251kv18 cy7c13121kv18 +1cy7c13141kv18	PDF
CY7C1314CV18 Abstract: CY7C1310CV18 CY7C1312CV18 CY7C1910CV18 CY7C1314CV18-250BZXC Contextual Info: CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■	Original	cy7c1310cv18 cy7c1910cv18 cy7c1312cv18 cy7c1314cv18 +218-mbit cy7c1314cv18-250bzxc	PDF
CY7C1310CV18 Abstract: CY7C1312CV18 CY7C1314CV18 CY7C1910CV18 Contextual Info: CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■	Original	cy7c1310cv18 cy7c1910cv18 cy7c1312cv18 cy7c1314cv18 +118-mbit	PDF
CY7C1312CV18 Abstract: CY7C1314CV18 Contextual Info: CY7C1312CV18 CY7C1314CV18 18-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1312CV18 – 1M x 18 CY7C1314CV18 – 512K x 36 ■ 250 MHz Clock for High Bandwidth	Original	cy7c1312cv18 cy7c1314cv18 18-mbit	PDF
CY7C1310AV18 Abstract: CY7C1312AV18 CY7C1314AV18 Contextual Info: CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses	Original	cy7c1310av18 cy7c1312av18 cy7c1314av18 18-mb +3167-mhz 167mhz cy7c1310av18/cy7c1312av18/cy7c1314av18	PDF
Contextual Info: CY7C1312CV18 CY7C1314CV18 18-Mbit QDR II SRAM 2-Word Burst Architecture 18-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1312CV18 – 1M x 18	Original	cy7c1312cv18 cy7c1314cv18 18-mbit	PDF

CY7C1312 Search Results

CY7C1312 Datasheets (63)

CY7C1312 Price and Stock

Infineon Technologies AG CY7C1312KV18-250BZXCT

Cypress Semiconductor CY7C1312BV18-167BZI

Cypress Semiconductor CY7C1312CV18-250BZC

Cypress Semiconductor CY7C1312CV18-167BZC

Cypress Semiconductor CY7C1312KV18-333BZC

CY7C1312 Datasheets Context Search

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CY7C1312BV18-167BZC

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CY7C1310AV18