310V18 Search Results

CY7C1310V18

Abstract: CY7C1312V18 CY7C1314V18
Contextual Info: 310V18 310V18 CY7C1312V18 CY7C1314V18 ADVANCE INFORMATION 18-Mb 2-Word Burst SRAM with QDR -II Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250 MHz Clock for High Bandwidth