CY7C1314JV18 Search Results
CY7C1314JV18 Datasheets (1)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| CY7C1314JV18-250BZXC |
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18 Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V | Original | 415.5KB | 26 |
CY7C1314JV18 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
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Contextual Info: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9 |
Original |
CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1312JV18 | |
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Contextual Info: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9 |
Original |
18-Mbit CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1910JV18 CY7C1312JV18 | |
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Contextual Info: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ |
Original |
CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1312JV18 | |
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Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-43127 Spec Title: CY7C1310JV18/CY7C1910JV18/CY7C1312JV18/ CY7C1314JV18, 18-MBIT QDR R -II SRAM 2WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 |
Original |
CY7C1310JV18/CY7C1910JV18/CY7C1312JV18/ CY7C1314JV18, 18-MBIT CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 |