CY7C1910KV18 Search Results
CY7C1910KV18 Datasheets Context Search
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Contextual Info: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310KV18 – 2 M x 8 ■ 333 MHz clock for high bandwidth |
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18-mbitcy7c1310kv18cy7c1910kv18cy7c1312kv18+1 | |
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Contextual Info: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions |
Original |
cy7c1310kv18cy7c1910kv18cy7c1312kv18cy7c1314kv18+1 | |
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Contextual Info: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions |
Original |
18-mbitcy7c1310kv18cy7c1910kv18cy7c1312kv18+1 | |
CY7C1312KV18-250BZXCContextual Info: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions |
Original |
18-mbitcy7c1310kv18cy7c1910kv18cy7c1312kv18+2 | |
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Contextual Info: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18 |
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18-mbitcy7c1312kv18cy7c1314kv18 | |
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Contextual Info: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Configurations Features Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18 |
Original |
cy7c1312kv18cy7c1314kv1818-mbit | |
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Contextual Info: CY7C1312KV18/CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18 |
Original |
cy7c1312kv18/cy7c1314kv1818-mbitcy7c1312kv18 |