S10031 Search Results

F100K

Abstract: J24E W24B AI 385 SMD b3 zb smd H11U
Contextual Info: & Semiconductor 100363 Low Power Dual 8-Input Multiplexer General Description 2000V ESD protection Pin/function com patible w ith 100163 The 100363 is a dual 8-input m ultiplexer. T he D ata Select Sn inputs determ ine which bit (A n and Bn) will be presented

Inventec VAIL 2.0

Abstract: PC9603 Inventec INVENTEC davos INVENTEC DAVOS 3.0 GST5009 C5761 Compaq P58 VSS28 CN5-001
Contextual Info: DAVOS-DF PV-1-BUILD 2004.11.04 EE DATE DATE POWER DRAWER DESIGN CHECK RESPONSIBLE DATE CHANGE NO. REV 3 SIZE = FILE NAME : XXXX-XXXXXX-XX P/N XXXXXXXXXXXX INVENTEC TITLE VER : DAVOS-DF SIZE CODE A3 CS SHEET DOC. NUMBER REV PC9603 1 A01 OF 65 TABLE OF CONTENTS

S10011

Abstract: S10045 S10046 S10035 S10110 S10063 S10071 S10100 S10090 S10115
Contextual Info: S10000 Series Fixed Chip Inductors for Space Applications FEATURES Military QPL Approved. Pick-and-place compatible. SPECIFICATIONS Met the requirements of MIL-PRF83446 and MIL-STD-981, class S or class B. Class S parts are intended for critical flight and mission-essential ground

Contextual Info: Semiconductor 100351 Low Power Hex D Flip-Flop General Description Features The • 4 0 % p o w e r re d u c tio n o f th e 100151 100 351 c o n ta in s s ix D -ty p e e d g e -trig g e re d , m a s te r/ s la v e flip -flo p s w ith tru e a n d c o m p le m e n t o u tp u ts , a p a ir o f

F100K

Abstract: J24E
Contextual Info: & Semiconductor 100323 Low Power Hex Bus Driver General Description The 100323 is a m onolithic device containing six bus drivers capable o f driving term inated lines with term inations as low as 25i l . To reduce crosstalk, each output has its own re­ spective ground connection. Transition tim es were designed

Contextual Info: • Baden-W iirttem berg Telegartner Technisches Buro Stuttgart Dipl.-lng. FH H. J. Schroedter W aldburgstraGe 104 D-70563 Stuttgart Tel: 0711-363-0300 Fax: 0711-363-0400 E-mail: hans-joerg.schroedter@ telegaertner.com Udo Rosch Bgm.-Grandauer-StraGe 5 D-83052 Bruckmuhl

Contextual Info: SPICE Device Model SiB457EDK Vishay Siliconix Dual P-Channel 20 V D-S MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C

SAA 1025

Abstract: F100K
Contextual Info: & Semiconductor 100344 Low Power 8-Bit Latch with Cut-Off Drivers General Description The 100344 contains eight D -type latches, individual inputs Dn , outputs (Q n), a com m on e n a ble pin (E), latch enable (LE), and output enable pin (OEN). A Q output follow s its D

65820

Contextual Info: SPICE Device Model SiS452DN Vishay Siliconix N-Channel 12 V D-S MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C

S10031

Abstract: SiR802DP
Contextual Info: SPICE Device Model SiR802DP Vishay Siliconix N-Channel 20 V D-S MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C

Contextual Info: SPICE Device Model SiR862DP Vishay Siliconix N-Channel 25 V D-S MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C

colour tv kit circuit diagram

Abstract: MS1003 MS1002-1 MS1003-1 MS1003-3 analogue signal delay line iw16
Contextual Info: MS 1003 MS1003 910 ELEMENT CCD ANALOGUE STORE T h e Plessey M S 100 3 is a c lo c k c o n tro lle d a n a lo g u e s h ift r e g is t e r f o r a p p lic a t i o n s i n c lu d i n g t im e d e la y , c o m p re s s io n /e x p a n s io n a n d te m p o ra ry s to ra g e o f a n a lo g u e

colour tv kit circuit diagram

Abstract: MS1002-1 MS1003 MS1003-1 MS1003-3 MS1002
Contextual Info: MS1003 MS1003 910 ELEMENT CCD ANALOGUE STORE T he Plessey M S1003 is a c lo c k c o n tro lle d an a lo g u e shift r e g is t e r f o r a p p lic a t i o n s in c lu d i n g t im e d e la y , c o m p re s s io n /e x p a n s io n and te m p o ra ry stora ge o f a na logue

F100K

Abstract: W16A
Contextual Info: & Semiconductor 100315 Low-Skew Quad Clock Driver General Description 1 D ifferential inputs and outputs S econdary clock available fo r system level testing 2000V ESD protection 1 V oltage com pensated operating range: - 4 .2 V to -5 .7 V 1 S tandard M icrocircuit Drawing