F100K Search Results

F100K

Abstract: L817
Contextual Info: F100194 Quint Duplex Bus Driver T ransceiver F100K ECL Product Description The F100194 is a qu in t line driver/receiver capable of transm itting and receiving fu ll duplex digital signals on ; high-speed bus line. Because o f the current source line driver, tw o independent messages may be transm itted

100325PC

Abstract: F100K M24B MO-047 MS-013 N24E V28A 100325QC 100325QI 100325SC
Contextual Info: Revised August 2000 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential

DS009879

Contextual Info: Revised November 1999 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential

Contextual Info: F100114 Quint Differential Line Receiver FAIRCHILD A Schlumberger Company F100K ECL Product Description The F100114 is a m on o lith ic q u in t differential line receiver w ith em itte r-fo llo w e r outputs. An internal reference supply V b b is available fo r single-ended

Contextual Info: * SYNERGY LOW-POWER HEX TTL-TO-PECL TRANSLATOR SY100S391 SEMICONDUCTOR DESCRIPTION FEATURES Operates from a single +5V supply Differential PECL outputs Companion chip to SY100S390 PECL-to-TTL translator Function and pinout compatible with National and Signetics F100K

333 045 01

Contextual Info: FAIRCHILD F 100122 A S chlum berger C om pari' ^ ^ ÎU ff l* F100K ECL Product Connection Diagrams Description The F100122 is a m on o lith ic 9-bit buffer. The device contains nine non-inverting buffer gates with single input and output. All inputs have 50 k i! pull-dow n

Contextual Info: F100165 Universal Priority Encoder FAIRCHILD A Schlumberger Company F100K ECL Product Description The F100165 contains eight input latches w ith a com m on Enable E follow ed by encoding logic w hich generates the binary address of the highest p rio rity input

Contextual Info: F100170 Universal Demultiplexer/ Decoder FAIRCHILD A S c h lu m b e rg e r C o m p a n y F100K ECL Product Description The F100170 universal dem ultiplexer/decoder functions as either a dual 1-of-4 decoder or as a single 1-of-8 decoder, depending on the signal applied to the M ode

Contextual Info: S E M IC O N D U C T O R tm 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex tra n sla tor fo r converting F100K logic levels to T T L logic levels. D ifferential inputs allo w each circuit to be used as an inverting, non-inverting or differential re­

7AC8

Contextual Info: F10474 1024 x 4-Bit Static Random Access Memory FA IR C H ILD A S chlum berger C om pany F100K ECL Product Description The F10474 is a 4096-bit read/w rite Random Access M em ory RAM , organized 1024 w ords by fo u r bits per w ord. It is designed for high-speed scratchpad, control

F100101

Abstract: PM710
Contextual Info: F100101 Triple 5-Input OR/NOR Gate FAIRCHILD A Schlumberger Company F100K ECL Product Description T he F100101 is a m on olithic triple 5-input O R/NOR gate. All inputs have 50 k i l p u ll-dow n resistors and all outputs are buffered. Connection Diagrams

Contextual Info: F100474 1024 x 4-Bit Static Random Access Memory FAIRCHILD A Schlumberger Company F100K ECL Product Description The F100474 is a 4096-bit read/w rite Random Access M em ory R AM , organized 1024 w ords by fo u r bits per w ord. It is designed fo r high-speed scratchpad, control

m3ub

Abstract: F100160
Contextual Info: F100160 Dual Parity Checker/Generator FAIRCHILD S c h lu m b e rg e r C o m p a n y A F100K ECL Product Connection Diagrams Description The F100160 is a dual parity checker/generator. Each half has nine inputs; the o utput is HIG H when an even num ber of inputs are HIGH. One of the nine inputs la or

Contextual Info: F A A I R C H I L F100150 Hex D Latch D S chlum berger C om pany F100K ECL Product Description The F100150 contains six D-type latches with true and com p le m e nt outputs, a pair o f C om m on Enables ~Ea and Eb , and a com m on Master Reset (MR). A Q output

100391PC

Abstract: 100391QC 100391QI 100391SC F100K M24B MO-047 MS-013 N24E V28A
Contextual Info: Revised August 2000 100391 Low Power Single Supply Hex TTL-to-PECL Translator General Description Features The 100391 is a hex translator for converting TTL logic levels to F100K PECL logic levels. The unique feature of this translator, is the ability to do this translation using only one

100393QC

Abstract: F100K MO-047 V28A
Contextual Info: Revised November 1999 100393 Low Power 9-Bit ECL-to-TTL Translator with Latches General Description Features The 100393 is a 9-bit translator for converting F100K logic levels to TTL logic levels. A LOW on the latch enable LE latches the data at the input state. A HIGH on the LE

PN generator circuit

Contextual Info: F100141 8-Bit Shift Register F100K ECL Product Connection Diagrams Description The F100141 contains eight edge-triggered, D-type flip-flops with individual inputs Pn and outputs (Qn) for parallel operation, and with serial inputs (D n) and steering logic for bidirectional shifting. The flip-flops

ODC4

Abstract: F100107
Contextual Info: F100107 Quint Exclusive OR/NOR Gate F100K ECL Product Description The F100107 is a monolithic quint exclusive-OR/NOR gate. The Function output is the wire-OR of all five exclusive-OR outputs: F = D1a D2a + (D1b D 2b) + (Di c © D 2c) + (D1d© D2d) + (D1e© D2e).

F100102DC

Contextual Info: F100102 Quint 2-Input OR/NOR Gate F100K ECL Product Connection Diagrams Description The F100102 is a monolithic quint 2-input OR/NOR gate with common enable. Ail inputs have 50 kO pull-down resistors and all outputs are buffered. Pin Names Dna- Dne E O a-O e

b37 diode

Abstract: C1995 F100K J24E M24B N24E V28A W24B 1380B
Contextual Info: 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels Differential inputs allow each circuit to be used as an inverting non-inverting or differential receiver An internal reference voltage generator provides

F100325

Abstract: F100125 F100K
Contextual Info: 100125 5251 N a tio n a l w im S e m ic o n d u c to r F100125 Hex ECL-to-TTL Translator General Description The F100125 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each cir­ cuit to be used as an inverting, non-inverting or differential

DIODE OA90

Abstract: OA90 diode eel -16-2005 F100K V28A
Contextual Info: EM ICDNDUCTOR t 100393 Low Power 9-Bit ECL-to-TTL Translator with Latches General Description Features The 100393 is a 9 -bit translator fo r converting F100K logic levels to FAST T T L logic levels. A LO W on the latch enable LE latches the d ata at the input state. A HIGH on the LE

100395QC

Abstract: F100K MO-047 V28A
Contextual Info: SEMICONDUCTOR Revised N ovem ber 1999 TM 100395 Low Power 9-Bit ECL-to-TTL Translator with Registers General Description Features The 100395 is a 9-bit translator for converting F100K logic levels to T T L logic levels. A HIGH on the output enable OE holds the T T L outputs in a high im pedance state. Two

F100K

Contextual Info: 100397 Quad Differential ECL/TTL Translating Transceiver with Latch General Description The 100397 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability