J24E Search Results

J24E

Contextual Info: 24 Lead 0 400 Wide Ceramic Dual-in-Line Package NS Package Number J24E All dimensions are in inches (millimeters) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

100336W-QMLV

Abstract: 100336FMQB 100136 100336DMQB 100336J-QMLV F100336 F336
Contextual Info: MILITARY DATA SHEET Original Creation Date: 10/30/95 Last Update Date: 10/21/96 Last Major Revision Date: 10/16/96 MN100336-X REV 2A0 4-STAGE COUNTER/SHIFT REGISTER General Description The F100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional

F364

Abstract: VM08 175C F100364
Contextual Info: & N a ti on al Semiconductor MILITARY DATA SHEET Original Creation Date: Last Update Date: Last Major Revision Date: M N 100364-X R E V 1A0 10/30/95 08/28/96 08/21/96 LOW P OWER 16-BIT M U L T IPLEXER General Description The F100364 is a 16— input multiplexer.

F100K

Abstract: J24E W24B AI 385 SMD b3 zb smd H11U
Contextual Info: & Semiconductor 100363 Low Power Dual 8-Input Multiplexer General Description 2000V ESD protection Pin/function com patible w ith 100163 The 100363 is a dual 8-input m ultiplexer. T he D ata Select Sn inputs determ ine which bit (A n and Bn) will be presented

F100K

Contextual Info: 100355 Low Power Quad Multiplexer/Latch General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable En inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D0 or

F100K

Abstract: J24E W24B
Contextual Info: October 19, 2009 100323 Low Power Hex Bus Driver General Description Features The 100323 is a monolithic device containing six bus drivers capable of driving terminated lines with terminations as low as 25Ω. To reduce crosstalk, each output has its own respective ground connection. Transition times were designed to be

F100K

Contextual Info: 100321 Low Power 9-Bit Inverter General Description The 100321 is a monolithic 9-bit inverter. The device contains nine inverting buffer gates with single input and output. All inputs have 50 kΩ pull-down resistors. n n n n n 2000V ESD protection Pin/function compatible with 100121

F100K

Contextual Info: 100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock CPC , and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct

Contextual Info: Se mi c o n dut July 1992 t o r 100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Com­ mon Clock CPc , and Master Set (MS) and Master Reset

smd marking d2d

Contextual Info: 100304 Low Power Quint AND/NAND Gate General Description The 100304 is monolithic quint AND/NAND gate. The Function output is the wire-NOR of all five AND gate outputs. All inputs have 50 kΩ pull-down resistors. n n n n n Features 2000V ESD protection Pin/function compatible with 100104

Contextual Info: 100355 Low Power Quad Multiplexer/Latch General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable En inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D0 or

16 input multiplexer

Contextual Info: 100364 Low Power 16-Input Multiplexer General Description The 100364 is a 16-input multiplexer. Data paths are controlled by four Select lines S0–S3 . Their decoding is shown in the truth table. Output data polarity is the same as the seleted input data. All inputs have 50 kΩ pulldown resistors.

Contextual Info: 100307 Low Power Quint Exclusive OR/NOR Gate General Description The 100307 is monolithic quint exclusive-OR/NOR gate. The Function output is the wire-OR of all five exclusive-OR outputs. All inputs have 50 kΩ pull-down resistors. n n n n n Features 2000V ESD protection

Contextual Info: A I R C H I I - D EMIC O N D U C T O R T 100351 Low Power Hex D Flip-Flop General Description Features The • 4 0 % p o w e r re d u c tio n o f th e 100151 100351 c o n ta in s s ix D -ty p e e d g e -trig g e re d , m a s te r/ s la v e flip -flo p s w ith tru e a n d c o m p le m e n t o u tp u ts , a p a ir o f

Contextual Info: S E M IC O N D U C T O R T M 100302 Low Power Quint 2-Input OR/NOR Gate General Description • 2000V ESD protection The 100302 is a m onolithic quint 2 -input O R /N O R gate with com m on enable. All inputs have 50 kQ pull-dow n resistors and all outputs are buffered.

Contextual Info: S E M IC O N D U C T O R tm 100322 Low Power 9-Bit Buffer General Description • 2000V ESD protection The 100322 is a m onolithic 9-bit buffer. The device contains nine non-inverting buffer gates w ith single input and output. All inputs have 50 kQ pull-down resistors and all outputs are

Contextual Info: S E M IC O N D U C T O R tm 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex tra n sla tor fo r converting F100K logic levels to T T L logic levels. D ifferential inputs allo w each circuit to be used as an inverting, non-inverting or differential re­

Contextual Info: S E M IC O N D U C T O R - r. 100398 Quad Differential ECL/TTL Translating Transceiver with Latch General Description to turn off w hen the high im pedance to duces term ination noise m argin w hen The 100398 is a quad latched tra n sce ive r designed to c o n ­

Contextual Info: Nationa I Semiconductor M ILITARY DATA SHEET MN100322-X REV OBO 0r g ^Lt nSte bS; oeSS Last Major Revision Date: 10/30/95 LOW POWER 9-BIT BUFFER General Description The 100322 is a monolithic 9-bit inverter. The device contains nine non-inverting buffer gates with single input and output.

b1565

Abstract: B1565 transistor 870b 24-Pin Plastic DIP B955 transistor b1565 C1995 F100K J24E N24E
Contextual Info: 100304 Low Power Quint AND NAND Gate General Description Features The 100304 is monolithic quint AND NAND gate The Function output is the wire-NOR of all five AND gate outputs All inputs have 50 kX pull-down resistors Y Y Y Y Y Y Logic Symbol Low Power Operation

b1565

Abstract: B1565 transistor E-HC C1995 F100K J24E V28A W24B Z0B Series
Contextual Info: 100370 Low Power Universal Demultiplexer Decoder General Description The 100370 universal demultiplexer decoder functions as either a dual 1-of-4 decoder or as a single 1-of-8 decoder depending on the signal applied to the Mode Control M input In the dual mode each half has a pair of active-LOW

b37 diode

Abstract: C1995 F100K J24E M24B N24E V28A W24B 1380B
Contextual Info: 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels Differential inputs allow each circuit to be used as an inverting non-inverting or differential receiver An internal reference voltage generator provides

B1565 transistor

Abstract: b1565 C1995 F100K J24E N24E V28A W24B D71011
Contextual Info: 100343 Low Power 8-Bit Latch General Description Features The 100343 contains eight D-type latches individual inputs Dn outputs (Qn) a common enable pin (E) and a latch enable pin (LE) A Q output follows its D input when both E and LE are LOW When either E or LE (or both) are HIGH a

100145

Abstract: 100145DC 100145FC J24E W24B
Contextual Info: 100145 National Jüâ Semiconductor 100145 16 x 4-Bit Register File Random Access Memory General Description T he 100145 is a 64-b it register file organized as 16 w ords o f four bits each. Separate address inputs fo r Read AR n and W rite (AW n) operations reduce overall cycle tim e by allow ­