W24B Search Results

W24B

Contextual Info: 24 Lead Cerquad NS Package Number W24B All dimensions are in inches millimeters LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

W24B04

Contextual Info: Preliminary W24B04 512K x 8 CMOS STATIC RAM 1. GENERAL DESCRIPTION The W24B04 is a normal-speed, very low-power CMOS static RAM organized as 524288 × 8 bits that operates on a wide voltage range from 2.7V to 3.6V power supply. The W24B04, W24B04-LE and W24B04-LI, can meet the requirement of various operating temperature. This device is manufactured

TSOP8

Abstract: 0105y
Contextual Info: Preliminary W24B02 256K x 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24B02 is a normal-speed, very low-power CMOS static RAM organized as 262144 x 8 bits that operates on a wide voltage range from 2.7V to 3.6V power supply. The W24B02, W24B02-LE and W24B02-LI, can meet the requirement of various operating temperature. This device is manufactured

100336W-QMLV

Abstract: 100336FMQB 100136 100336DMQB 100336J-QMLV F100336 F336
Contextual Info: MILITARY DATA SHEET Original Creation Date: 10/30/95 Last Update Date: 10/21/96 Last Major Revision Date: 10/16/96 MN100336-X REV 2A0 4-STAGE COUNTER/SHIFT REGISTER General Description The F100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional

F100K

Abstract: J24E W24B
Contextual Info: October 19, 2009 100323 Low Power Hex Bus Driver General Description Features The 100323 is a monolithic device containing six bus drivers capable of driving terminated lines with terminations as low as 25Ω. To reduce crosstalk, each output has its own respective ground connection. Transition times were designed to be

F100K

Contextual Info: 100321 Low Power 9-Bit Inverter General Description The 100321 is a monolithic 9-bit inverter. The device contains nine inverting buffer gates with single input and output. All inputs have 50 kΩ pull-down resistors. n n n n n 2000V ESD protection Pin/function compatible with 100121

F100K

Contextual Info: 100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock CPC , and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct

Contextual Info: Se mi c o n dut July 1992 t o r 100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Com­ mon Clock CPc , and Master Set (MS) and Master Reset

smd marking d2d

Contextual Info: 100304 Low Power Quint AND/NAND Gate General Description The 100304 is monolithic quint AND/NAND gate. The Function output is the wire-NOR of all five AND gate outputs. All inputs have 50 kΩ pull-down resistors. n n n n n Features 2000V ESD protection Pin/function compatible with 100104

16 input multiplexer

Contextual Info: 100364 Low Power 16-Input Multiplexer General Description The 100364 is a 16-input multiplexer. Data paths are controlled by four Select lines S0–S3 . Their decoding is shown in the truth table. Output data polarity is the same as the seleted input data. All inputs have 50 kΩ pulldown resistors.

Contextual Info: 100307 Low Power Quint Exclusive OR/NOR Gate General Description The 100307 is monolithic quint exclusive-OR/NOR gate. The Function output is the wire-OR of all five exclusive-OR outputs. All inputs have 50 kΩ pull-down resistors. n n n n n Features 2000V ESD protection

CS16LV40963

Abstract: BS62LV4006 sram cross reference CS18LV40963 LY6264 Hynix Cross Reference cs18lv10245 cs18lv02560 LY621024 K6X1008C2D
Contextual Info: www.ashlea.co.uk 01793 783784 Low power SRAM Cross Reference Density Configuration 64K 8Kx8 256K 32Kx8 Lyontek LY6264 LY62L64 LY62256 LY62L256 LY62256 2.7-5.5 1M 128Kx8 64Kx16 LY621024 LY62L1024 LY62L6416 Samsung K6X0808C1D K6X0808T1D K6X1008C2D K6X1008T2D

Contextual Info: A I R C H I I - D EMIC O N D U C T O R T 100351 Low Power Hex D Flip-Flop General Description Features The • 4 0 % p o w e r re d u c tio n o f th e 100151 100351 c o n ta in s s ix D -ty p e e d g e -trig g e re d , m a s te r/ s la v e flip -flo p s w ith tru e a n d c o m p le m e n t o u tp u ts , a p a ir o f

Contextual Info: S E M IC O N D U C T O R tm 100354 Low Power 8-Bit Register with Cut-Off Drivers General Description The 100354 contains eight D-Type edge triggered, master/ slave flip-flops with individual inputs Dn , true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a com­

b1565

Abstract: B1565 transistor 870b 24-Pin Plastic DIP B955 transistor b1565 C1995 F100K J24E N24E
Contextual Info: 100304 Low Power Quint AND NAND Gate General Description Features The 100304 is monolithic quint AND NAND gate The Function output is the wire-NOR of all five AND gate outputs All inputs have 50 kX pull-down resistors Y Y Y Y Y Y Logic Symbol Low Power Operation

b1565

Abstract: B1565 transistor E-HC C1995 F100K J24E V28A W24B Z0B Series
Contextual Info: 100370 Low Power Universal Demultiplexer Decoder General Description The 100370 universal demultiplexer decoder functions as either a dual 1-of-4 decoder or as a single 1-of-8 decoder depending on the signal applied to the Mode Control M input In the dual mode each half has a pair of active-LOW

b37 diode

Abstract: C1995 F100K J24E M24B N24E V28A W24B 1380B
Contextual Info: 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels Differential inputs allow each circuit to be used as an inverting non-inverting or differential receiver An internal reference voltage generator provides

B1565 transistor

Abstract: b1565 C1995 F100K J24E N24E V28A W24B D71011
Contextual Info: 100343 Low Power 8-Bit Latch General Description Features The 100343 contains eight D-type latches individual inputs Dn outputs (Qn) a common enable pin (E) and a latch enable pin (LE) A Q output follows its D input when both E and LE are LOW When either E or LE (or both) are HIGH a

100331DMQB

Abstract: 100331FMQB 100331J-QMLV 100331WFQMLV 100331W-QMLV 5962-9153601MXA F100331 5962-9153601vya
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 10/30/95 Last Update Date: 04/23/04 Last Major Revision Date: 08/21/96 MN100331-X REV 1B0 LOW POWER TRIPLE D FLIP-FLOP General Description The F100331 contains three D-type, edge-triggered master/slave flip-flops with true and

ns108

Abstract: F100K
Contextual Info: S E M IC O N D U C T O R tm 100321 Low Power 9-Bit Inverter General Description The 100321 is a m onolithic 9-bit inverter. The device con tains nine inverting buffer gates with single input and output All inputs have 50 kQ pull-dow n resistors. • 2000V ESD protection

F100K

Contextual Info: Semiconductor July 1992 100363 Low Power Dual 8-Input Multiplexer General Description Features The 100363 is a dual 8-input m ultiplexer. The D ata S elect Sn inputs determ ine w hich bit (An and Bn) w ill be prese n t­ ed at th e o utputs (Za and Z b respectively). The sam e bit

DM74AS646

Abstract: DM74AS646NT DM74AS646WM DM74AS648NT DM74AS648WM M24B N24C
Contextual Info: E M IC D N D U C T O R t DM74AS646/DM74AS648 Octal Bus Transceiver and Register General Description This device incorporates an octal bus transceiver and an oc­ tal D-type register configured to enable multiplexed trans­ mission of data from bus to bus or internal register to bus.

mr 6710

Abstract: DI 762 F100K
Contextual Info: EM ICDNDUCTOR t 100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D -type, edge-triggered m aster/ slave flip-flops with true and com plem ent outputs, a C om ­ mon C lock CPc , and M aster Set (MS) and M aster Reset

ha 1555

Abstract: F100K J24E N24E 7B223
Contextual Info: S E M IC O N D U C T O R tm 100360 Low Power Dual Parity Checker/Generator General Description Features The 100360 is a dual parity checker/generator. Each half has nine inputs; the output Is HIGH when an even num ber of in­ puts are HIGH. One of the nine inputs la or lb has the