F1001 Search Results

F100122

Abstract: F100322
Contextual Info: 100122 a National Semiconductor F100122 9-B it B uffer General Description The F100122 is a m o nolithic 9-bit buffer. Th e device co n ­ tains nine non-inverting buffer gates w ith single input and o u tp u t All inputs have 50 k f l pull-dow n re sistors and all

F100K

Abstract: L817
Contextual Info: F100194 Quint Duplex Bus Driver T ransceiver F100K ECL Product Description The F100194 is a qu in t line driver/receiver capable of transm itting and receiving fu ll duplex digital signals on ; high-speed bus line. Because o f the current source line driver, tw o independent messages may be transm itted

Contextual Info: F100114 Quint Differential Line Receiver FAIRCHILD A Schlumberger Company F100K ECL Product Description The F100114 is a m on o lith ic q u in t differential line receiver w ith em itte r-fo llo w e r outputs. An internal reference supply V b b is available fo r single-ended

333 045 01

Contextual Info: FAIRCHILD F 100122 A S chlum berger C om pari' ^ ^ ÎU ff l* F100K ECL Product Connection Diagrams Description The F100122 is a m on o lith ic 9-bit buffer. The device contains nine non-inverting buffer gates with single input and output. All inputs have 50 k i! pull-dow n

Contextual Info: F100165 Universal Priority Encoder FAIRCHILD A Schlumberger Company F100K ECL Product Description The F100165 contains eight input latches w ith a com m on Enable E follow ed by encoding logic w hich generates the binary address of the highest p rio rity input

Contextual Info: F100170 Universal Demultiplexer/ Decoder FAIRCHILD A S c h lu m b e rg e r C o m p a n y F100K ECL Product Description The F100170 universal dem ultiplexer/decoder functions as either a dual 1-of-4 decoder or as a single 1-of-8 decoder, depending on the signal applied to the M ode

Contextual Info: F100141 8-Bit Shift Register FAIRCHILD A S chlum berger C om pany FIOOK E C L P ro d u c t C onnection D iagram s D escription T h e F100141 c o n ta in s e ig h t e d g e -trig g e re d , D -ty p e 24-P in D IP T o p V iew flip -flo p s w ith in d iv id u a l in p u ts (P n ) and o u tp u ts (Q n ) fo r

F100101

Abstract: PM710
Contextual Info: F100101 Triple 5-Input OR/NOR Gate FAIRCHILD A Schlumberger Company F100K ECL Product Description T he F100101 is a m on olithic triple 5-input O R/NOR gate. All inputs have 50 k i l p u ll-dow n resistors and all outputs are buffered. Connection Diagrams

m3ub

Abstract: F100160
Contextual Info: F100160 Dual Parity Checker/Generator FAIRCHILD S c h lu m b e rg e r C o m p a n y A F100K ECL Product Connection Diagrams Description The F100160 is a dual parity checker/generator. Each half has nine inputs; the o utput is HIG H when an even num ber of inputs are HIGH. One of the nine inputs la or

Contextual Info: F A A I R C H I L F100150 Hex D Latch D S chlum berger C om pany F100K ECL Product Description The F100150 contains six D-type latches with true and com p le m e nt outputs, a pair o f C om m on Enables ~Ea and Eb , and a com m on Master Reset (MR). A Q output

Contextual Info: F100181 4-BIT BINARY/BCD ALU F100K SERIES ECL DESCRIPTION - The F100181 performs eight logic operations and eight arithmetic op-j. erations on a pair of 4-bit words. The operating mode is determined by signals appliejjIJojJ the Select Sn inputs, as shown in the Function Select table. In addition to per1—

PN generator circuit

Contextual Info: F100141 8-Bit Shift Register F100K ECL Product Connection Diagrams Description The F100141 contains eight edge-triggered, D-type flip-flops with individual inputs Pn and outputs (Qn) for parallel operation, and with serial inputs (D n) and steering logic for bidirectional shifting. The flip-flops

ODC4

Abstract: F100107
Contextual Info: F100107 Quint Exclusive OR/NOR Gate F100K ECL Product Description The F100107 is a monolithic quint exclusive-OR/NOR gate. The Function output is the wire-OR of all five exclusive-OR outputs: F = D1a D2a + (D1b D 2b) + (Di c © D 2c) + (D1d© D2d) + (D1e© D2e).

F100102DC

Contextual Info: F100102 Quint 2-Input OR/NOR Gate F100K ECL Product Connection Diagrams Description The F100102 is a monolithic quint 2-input OR/NOR gate with common enable. Ail inputs have 50 kO pull-down resistors and all outputs are buffered. Pin Names Dna- Dne E O a-O e

BIT 3195 G

Abstract: F100179 F100180
Contextual Info: 100180 National Semiconductor F100180 High-Speed 6-Bit Adder General Description The F100180 is a high-speed 6 -bit adder capable of per­ forming a full 6 -bit addition of two operands. Inputs for the adder are active-LOW Carry, Operand A, and Operand B;

F100170

Abstract: F100370
Contextual Info: 100170 f/WA National dtüm Semiconductor F100170 Universal Demultiplexer/Decoder General Description The F100170 universal d em u ltip le xe r/d eco d e r fu n ctio ns as eithe r a dual 1 -of-4 deco d e r o r as a single 1 -o f-8 decoder, depending on the signal applied to the Mode C ontrol M

fairchild ECL

Abstract: ECL Decade Counter F10010 F10016 ECL binary Counter ecl 10016
Contextual Info: Fiooic/» FlOOie^ BCD DECADE COUNTER/4-BIT BINARY COUNTER GENERAL DESCRIPTION — The F10010 is a high-speed synchronous, presettable. cascadable BCD Decade Counter and the F10016 is a high-speed synchronous, pre­ settable, cascadable 4-Bit Binary Counter. They are m u ltifu n ctio n MSI building

F100179

Abstract: F100180 F100181 9871
Contextual Info: 100179 £ 5 | National Æ Â Semiconductor F100179 Carry Lookahead Generator General Description The F100179 is a high-speed Carry Lookahead G enerator intended fo r use with th e F100180 6 -bit fa st A d d er and the F100181 4-bit ALU. All inputs have 50 k i l pulldow n resis­

IC-415

Abstract: F100171 F100371
Contextual Info: 100171 fjW\ National ÆA Semiconductor F100171 Triple 4-Input Multiplexer with Enable General Description The F100171 co nta in s three 4-input m ultiplexers which share a com m on decoder inputs So and S-i . O utput buffer gates provide true and co m ple m e nt outputs. A HIGH on the

F100124

Abstract: F100324 Hex TTL-to-ECL Translator F100124
Contextual Info: 100124 National éüA Semiconductor F100124 Hex TTL-to-ECL Translator General Description The F100124 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are com­ patible with standard or Schottky TTL. A common Enable

F100325

Abstract: F100125 F100K
Contextual Info: 100125 5251 N a tio n a l w im S e m ic o n d u c to r F100125 Hex ECL-to-TTL Translator General Description The F100125 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each cir­ cuit to be used as an inverting, non-inverting or differential

F100164

Abstract: F100364
Contextual Info: 100164 ZWA National mUrn Semiconductor F100164 16-Input Multiplexer General Description The F100164 is a 16-input multiplexer. Data paths are con­ trolled by four Select lines S0 - S 3 . Their decoding is shown in the truth table. Output data polarity is the same as the

F100125

Contextual Info: 100125 KM National Juä Semiconductor F100125 Hex ECL-to-TTL Translator General Description The F100125 is a hex tra n sla tor fo r converting F100K logic levels to TTL logic levels. D ifferential inputs allow each cir­ cuit to be used as an inverting, non-inverting or differential

Contextual Info: 100113 National Semiconductor F100113 Quad Driver General Description The F100113 is a monolithic quad driver with two OR and two NOR outputs and common enable. The common input is buffered to minimize input loading. If the D inputs are not used the Enable can be used to drive sixteen 5011 lines. All