DQ8DQ15 Search Results

tr8c

Abstract: TMS28F200
Contextual Info: TMS28F20ÛBZT, TMS28F200BZB 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SWS2dOO - JUNE 1 9 9 4 - REVISED SEPTEMBER 1997 • ■ I I I • • • • • • • • • • Organization . . . 262144 by 8 bits 131072 by 16 bits Array-Blocking Architecture

Video RAM

Abstract: TMS55165
Contextual Info: TMS55165 262144 BY 16-BIT MULTIPORT VIDEO RAM SMVS165B-AUGUST1992-flEVISED JANUARY 1993 DGH PACKAGEt TOP VIEW DRAM : 262 144 Words x 16 Bits SAM: 256 Words x 16 Bits Dual Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and SAM Ports

lm814

Abstract: ID32-001
Contextual Info: TOSHIBA TC59LM814/06BFT-22,-24,-30 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM814/06BFT are a CMOS Double Data Rate Fast Cycle Random Access Memory DDR

00F1H

Contextual Info: • v p a c _MX29F1 610 1 B M -B IT C 2 M x S / 1 M x 1 6 C M O S S IN G U E V O L T A G E F L A S H E E P R O M FEATURES • • • • • • • • • 5V ± 10% write and erase JEDEC-standard EEPROM commands Minimum 1,000/10,000 write/erase cycles

IS42VS16100E

Abstract: 42VS16100E IS42VS16100E-75BLI
Contextual Info: IS42VS16100E 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 133, 100, 83 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11

Contextual Info: TMS55160 262144 BY 16-BIT MULTIPORT VIDEO RAM SMVS160B-AUGUST1992-REVISED JANUARY 1993 * * * * * DGH PACKAGEt DRAM : 262144 Words x 16 Bits SAM: 256 Words x 16 Bits TOP VIEW Dual Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and

Contextual Info: TMS416160, TMS416160P 1 048 576-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES SMKS660-DECEMBER 1992 Organization. . . 1 048 576 x 16 RE P A C K A G E t DC P A C K AG E t TOP VIEW (TOP VIEW) Single 5-V Supply (10% Tolerance) '416160/P-60 '416160/P-70

AS8S512K3

Contextual Info: ADVANCED iPEM 64 Mb ASYNC SRAM AS8S2M32PEC 64Mb, 2Mx32 CMOS 3.3V, High Speed Static RAM Integrated Plastic Encapsulated Microcircuit FEATURES DESCRIPTION Integrated Real-Time Memory Array Solution No latency or refresh cycles Parallel Read/Write Interface

AS4SD32M16

Contextual Info: SDRAM AS4SD32M16 512Mb: 32 Meg x 16 SDRAM PIN ASSIGNMENT Top View Synchronous DRAM Memory 54-Pin TSOP FEATURES • Full Military temp (-55°C to 125°C) processing available • Configuration: 32 Meg x 16 (8 Meg x 16 x 4 banks) • Fully synchronous; all signals registered on positive

Contextual Info: iPEM 2.4Gb SDRAM-DDR AS4DDR32M72PBG1 32Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES BENEFITS DDR SDRAM Data Rate = 200, 250, 266, 333Mbps Package: • 208 Plastic Ball Grid Array PBGA , 16 x 23mm-1.0mm pitch 2.5V ±0.2V core power supply

Contextual Info: SDRAM AS4SD8M16 128 Mb: 8 Meg x 16 SDRAM PIN ASSIGNMENT Top View Synchronous DRAM Memory 54-Pin TSOP FEATURES • • • • • • • • • • • • • • Full Military temp (-55°C to 125°C) processing available Copper lead frame option for enhanced reliability

w19b320

Contextual Info: W19B320AT/B Data Sheet 4M x 8/2M × 16 BITS 3V FLEXIBLE BANK FLASH MEMORY Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

M29W320DT

Abstract: M29W320D M29W320DB TFBGA48
Contextual Info: M29W320DT M29W320DB 32 Mbit 4Mb x8 or 2Mb x16, Boot Block 3V Supply Flash Memory FEATURES SUMMARY • SUPPLY VOLTAGE Figure 1. Packages – VCC = 2.7V to 3.6V for Program, Erase and Read – VPP =12V for Fast Program (optional) ■ ACCESS TIME: 70, 90ns

NT5TU128M8DE

Abstract: NT5TU64M16DG nt5tu64m16dg-Bd NT5TU128M8DE-BD NT5TU256M4DE nt5tu64m NT5TU64M16 NT5TU64M16DG-3C NT5TU64M16DG-3CI NT5TU64M16DG-BE
Contextual Info: NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG NT5TB256M4DE / NT5TB128M8DE / NT5TB64M16DG 1Gb DDR2 SDRAM Feature CAS Latency Frequency -37B/-37BI -3C/-3CI -AD/-ADI -AC/-ACI/-ACL -BE -BD DDR2-533 DDR2-667 DDR2-800 DDR2-800 DDR2-1066 DDR2-1066 4-4-4 5-5-5 6-6-6

NT5DS8M16FS-5T

Abstract: NT5DS8M16FS-6K NT5DS8
Contextual Info: NT5DS8M16FT NT5DS8M16FS 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2 & 2.5 for 6K, 2, 2.5, & 3 for 5T

Nanya nt5ds8m16fs

Abstract: NT5DS8M16FS NT5DS8M16FT-5TI NT5DS8M16FS-5T DDR333 DDR400 NT5DS8M16 NT5DS8M16FT-6KI NT5DS8M16FT
Contextual Info: NT5DS8M16FT-5TI NT5DS8M16FS-5TI NT5DS8M16FT-6KI NT5DS8M16FS-6KI 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8

NT5DS8M16FS-5T

Abstract: NT5DS8M16FS-6K NT5DS8M16 NT5DS8M16FS
Contextual Info: NT5DS8M16FT NT5DS8M16FS 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2 & 2.5 for 6K, 2, 2.5, & 3 for 5T

NT5DS16M16BF-6K

Abstract: NT5DS32M8BT NT5DS16M16BT-6K NT5DS16M16BT NT5DS64M4BT NT5DS32M
Contextual Info: NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Features • Data mask DM for write data • DLL aligns DQ and DQS transitions with CK transitions

K4T51043QB-GCCC

Abstract: K4T51043QB-GCE6 K4T51043QB-GLE6
Contextual Info: Preliminary DDR2 SDRAM 512Mb B-die DDR2 SDRAM 512Mb B-die DDR2 SDRAM Specification Version 0.91 September 2003 Rev. 0.91 Sep. 2003 Page 1 of 38 Preliminary DDR2 SDRAM 512Mb B-die DDR2 SDRAM Contents 1. Key Feature 2. Package Pinout/Mechnical Dimension & Addressing

tmp95fy64

Abstract: TMP95FY64F tmp95fy CT 55H TLCS-90 LFFP100-P-1414-0 95fy64 QFP100P
Contextual Info: CMOS 16-bit Microcontroller TMP95FY64F Page 1 of 92 This is the html version of the file . G o o g l e automatically generates html versions of documents as we crawl the web. To link to or bookmark this page, use the following url:

09005aef811ce1d5

Abstract: MT48LC2M32B2 MT48LC2M32B2TG-7G
Contextual Info: 64Mb: x32 SDRAM SYNCHRONOUS DRAM MT48LC2M32B2 - 512K x 32 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdramds FEATURES • PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock

TME 87 0D

Contextual Info: SIEMENS 3.3V 8M x 64-Bit EDO-DRAM Module 3.3V 8M x 72-Bit EDO-DRAM Module HYM64V8005GU-50/-60 HYM64V8045GU-50/-60 HYM72V8005GU-50/-60 HYM72V8045GU-50/-60 168pin unbuffered DIMM Module with serial presence detect * 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module

MT48LC8M32LFB5

Abstract: D9CDF MT48H8M32LFB5-75 IT mt48h8m32lff5-8 MT48H8M32LFB5-75 MT48H8M32LF MT48V8M32LFB5-10 MT48LC8M32LFB5-8 stop mt48h8m32lfb5 rev g
Contextual Info: 256Mb: x32 Mobile SDRAM Features Mobile SDRAM MT48LC8M32LF, MT48V8M32LF, MT48H8M32LF - 2 Meg x 32 x 4 banks For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/dram/mobile Features • • • • • • • • • • • •

256mb ddr333 200 pin

Abstract: DDR266 DDR266A DDR266B DDR333 K4H560438D-GC K4H561638D
Contextual Info: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition